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| author | Wang Dongsheng <dongsheng.wang@freescale.com> | 2013-12-17 16:17:01 +0800 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-01-07 19:40:28 -0600 |
| commit | 1d47ddf7c3725e889763b1fffa70a04e1061940b (patch) | |
| tree | ab109ea6d4c9f052c6515b1b0c40659076a4d1f3 /arch/powerpc/kernel/cpu_setup_fsl_booke.S | |
| parent | 202e059ce34d5c5e3ff8a542866c280d575ccb17 (diff) | |
| download | linux-1d47ddf7c3725e889763b1fffa70a04e1061940b.tar.gz linux-1d47ddf7c3725e889763b1fffa70a04e1061940b.tar.bz2 linux-1d47ddf7c3725e889763b1fffa70a04e1061940b.zip | |
powerpc/85xx: add hardware automatically enter pw20 state
Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/kernel/cpu_setup_fsl_booke.S')
| -rw-r--r-- | arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 26c09db2ec20..cc2d8962e090 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -55,6 +55,25 @@ _GLOBAL(__e500_dcache_setup) /* * FIXME - we haven't yet done testing to determine a reasonable default + * value for PW20_WAIT_IDLE_BIT. + */ +#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */ +_GLOBAL(setup_pw20_idle) + mfspr r3, SPRN_PWRMGTCR0 + + /* Set PW20_WAIT bit, enable pw20 state*/ + ori r3, r3, PWRMGTCR0_PW20_WAIT + li r11, PW20_WAIT_IDLE_BIT + + /* Set Automatic PW20 Core Idle Count */ + rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT + + mtspr SPRN_PWRMGTCR0, r3 + + blr + +/* + * FIXME - we haven't yet done testing to determine a reasonable default * value for AV_WAIT_IDLE_BIT. */ #define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */ @@ -83,6 +102,7 @@ _GLOBAL(__setup_cpu_e6500) bl .setup_lrat_ivor 1: #endif + bl setup_pw20_idle bl setup_altivec_idle bl __setup_cpu_e5500 mtlr r6 @@ -151,6 +171,7 @@ _GLOBAL(__restore_cpu_e6500) beq 1f bl .setup_lrat_ivor 1: + bl .setup_pw20_idle bl .setup_altivec_idle bl __restore_cpu_e5500 mtlr r5 |