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| author | LEROY Christophe <christophe.leroy@c-s.fr> | 2014-09-19 10:36:09 +0200 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-11-07 18:10:44 -0600 |
| commit | c9a803fb17bcec0e7527dc8fa055e56a9691abbb (patch) | |
| tree | aa2c8292bc4d3a7999b21b9bf5d3f90838129b4a /arch/powerpc | |
| parent | 4094f28f90adab007eca9babf28f606a40a83032 (diff) | |
| download | linux-c9a803fb17bcec0e7527dc8fa055e56a9691abbb.tar.gz linux-c9a803fb17bcec0e7527dc8fa055e56a9691abbb.tar.bz2 linux-c9a803fb17bcec0e7527dc8fa055e56a9691abbb.zip | |
powerpc/8xx: _PMD_PRESENT already set in level 1 entries
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 8d6e6830a675..46b47e1fe2a9 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -342,7 +342,6 @@ InstructionTLBMiss: /* We have a pte table, so load the MI_TWC with the attributes * for this "segment." */ - ori r11,r11,1 /* Set valid bit */ MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */ mfspr r11, SPRN_SRR0 /* Get effective address of fault */ /* Extract level 2 index */ @@ -419,7 +418,6 @@ DataStoreTLBMiss: rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ lwz r10, 0(r10) /* Get the pte */ - ori r11, r11, 1 /* Set valid bit in physical L2 page */ /* Insert the Guarded flag into the TWC from the Linux PTE. * It is bit 27 of both the Linux PTE and the TWC (at least * I got that right :-). It will be better when we can put |