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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2005-11-07 14:27:33 +1100 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2005-11-08 11:17:34 +1100 |
| commit | 4350147a816b9c5b40fa59e4fa23f17490630b79 (patch) | |
| tree | c333986047de60aa90809d669895726610c0c3e5 /arch/ppc64 | |
| parent | a82765b6eee3d1267ded3320ca67b39fe1844599 (diff) | |
| download | linux-4350147a816b9c5b40fa59e4fa23f17490630b79.tar.gz linux-4350147a816b9c5b40fa59e4fa23f17490630b79.tar.bz2 linux-4350147a816b9c5b40fa59e4fa23f17490630b79.zip | |
[PATCH] ppc64: SMU based macs cpufreq support
CPU freq support using 970FX powertune facility for iMac G5 and SMU
based single CPU desktop.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc64')
| -rw-r--r-- | arch/ppc64/Kconfig | 10 | ||||
| -rw-r--r-- | arch/ppc64/kernel/misc.S | 72 |
2 files changed, 81 insertions, 1 deletions
diff --git a/arch/ppc64/Kconfig b/arch/ppc64/Kconfig index 2130cc315957..94a81279deac 100644 --- a/arch/ppc64/Kconfig +++ b/arch/ppc64/Kconfig @@ -173,6 +173,16 @@ config KEXEC support. As of this writing the exact hardware interface is strongly in flux, so no good recommendation can be made. +source "drivers/cpufreq/Kconfig" + +config CPU_FREQ_PMAC64 + bool "Support for some Apple G5s" + depends on CPU_FREQ && PMAC_SMU && PPC64 + select CPU_FREQ_TABLE + help + This adds support for frequency switching on Apple iMac G5, + and some of the more recent desktop G5 machines as well. + config IBMVIO depends on PPC_PSERIES || PPC_ISERIES bool diff --git a/arch/ppc64/kernel/misc.S b/arch/ppc64/kernel/misc.S index 077507ffbab8..914632ec587d 100644 --- a/arch/ppc64/kernel/misc.S +++ b/arch/ppc64/kernel/misc.S @@ -560,7 +560,7 @@ _GLOBAL(real_readb) isync blr - /* +/* * Do an IO access in real mode */ _GLOBAL(real_writeb) @@ -593,6 +593,76 @@ _GLOBAL(real_writeb) #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */ /* + * SCOM access functions for 970 (FX only for now) + * + * unsigned long scom970_read(unsigned int address); + * void scom970_write(unsigned int address, unsigned long value); + * + * The address passed in is the 24 bits register address. This code + * is 970 specific and will not check the status bits, so you should + * know what you are doing. + */ +_GLOBAL(scom970_read) + /* interrupts off */ + mfmsr r4 + ori r0,r4,MSR_EE + xori r0,r0,MSR_EE + mtmsrd r0,1 + + /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits + * (including parity). On current CPUs they must be 0'd, + * and finally or in RW bit + */ + rlwinm r3,r3,8,0,15 + ori r3,r3,0x8000 + + /* do the actual scom read */ + sync + mtspr SPRN_SCOMC,r3 + isync + mfspr r3,SPRN_SCOMD + isync + mfspr r0,SPRN_SCOMC + isync + + /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah + * that's the best we can do). Not implemented yet as we don't use + * the scom on any of the bogus CPUs yet, but may have to be done + * ultimately + */ + + /* restore interrupts */ + mtmsrd r4,1 + blr + + +_GLOBAL(scom970_write) + /* interrupts off */ + mfmsr r5 + ori r0,r5,MSR_EE + xori r0,r0,MSR_EE + mtmsrd r0,1 + + /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits + * (including parity). On current CPUs they must be 0'd. + */ + + rlwinm r3,r3,8,0,15 + + sync + mtspr SPRN_SCOMD,r4 /* write data */ + isync + mtspr SPRN_SCOMC,r3 /* write command */ + isync + mfspr 3,SPRN_SCOMC + isync + + /* restore interrupts */ + mtmsrd r5,1 + blr + + +/* * Create a kernel thread * kernel_thread(fn, arg, flags) */ |