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| author | Alan Kao <alankao@andestech.com> | 2018-04-20 07:27:49 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-06-04 14:02:01 -0700 |
| commit | 178e9fc47aaec1b8952b553444e94802d7570599 (patch) | |
| tree | efa3bc88ef7dfdad550960dc9413ebdcda32727d /arch/riscv/Kconfig | |
| parent | 29dcea88779c856c7dc92040a0c01233263101d4 (diff) | |
| download | linux-178e9fc47aaec1b8952b553444e94802d7570599.tar.gz linux-178e9fc47aaec1b8952b553444e94802d7570599.tar.bz2 linux-178e9fc47aaec1b8952b553444e94802d7570599.zip | |
perf: riscv: preliminary RISC-V support
This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles. Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.
riscv_base_pmu should be able to run on any RISC-V machine that
conforms to the Priv-Spec. Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes. Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.
Cc: Nick Hu <nickhu@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Signed-off-by: Alan Kao <alankao@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index cd4fd85fde84..4495604394e5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -25,6 +25,7 @@ config RISCV select HAVE_DMA_API_DEBUG select HAVE_DMA_CONTIGUOUS select HAVE_GENERIC_DMA_COHERENT + select HAVE_PERF_EVENTS select IRQ_DOMAIN select NO_BOOTMEM select RISCV_ISA_A if SMP @@ -198,6 +199,19 @@ config RISCV_ISA_C config RISCV_ISA_A def_bool y +menu "supported PMU type" + depends on PERF_EVENTS + +config RISCV_BASE_PMU + bool "Base Performance Monitoring Unit" + def_bool y + help + A base PMU that serves as a reference implementation and has limited + feature of perf. It can run on any RISC-V machines so serves as the + fallback, but this option can also be disable to reduce kernel size. + +endmenu + endmenu menu "Kernel type" |