Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (72 commits)
  sh: SuperH Mobile CEU and camera platform data for AP325RXA
  sh: Update smc911x platform data for AP325RXA
  sh: SuperH Mobile LCDC platform data for AP325RXA
  sh: Add SuperH Mobile CEU platform data for Migo-R
  sh: Add SuperH Mobile LCDC platform data for Migo-R
  sh: Move asid_cache() out of ifdef to fix SH-3/4 nommu build.
  sh: Workaround for __put_user_asm() bug with gcc 4.x on big-endian.
  sh: Wire up new syscalls.
  sh: fix uImage Entry Point
  sh_keysc: remove request_mem_region() and release_mem_region()
  sh: Don't miss pending signals returning to user mode after signal processing
  sh: Use clk_always_enable() on sh7366
  sh: Use clk_always_enable() on sh7343 / SE77343
  sh: Use clk_always_enable() on sh7722 / Migo-R / SE7722
  sh: Use clk_always_enable() on sh7723 / ap325rxa
  sh: Introduce clk_always_enable() function
  sh: Show all clocks and their state in /proc/clocks
  sh: Merge sh7343 and sh7722 clock code
  sh: Add SuperH Mobile MSTPCR bits to clock framework
  sh: Use arch_flags to simplify sh7722 siu clock code
  ...

1 files changed, 46 insertions, 0 deletions

diff --git a/arch/sh/drivers/pci/fixups-sh7785lcr.c b/arch/sh/drivers/pci/fixups-sh7785lcr.c
new file mode 100644
index 000000000000..4949e601387a
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-sh7785lcr.c
@@ -0,0 +1,46 @@
+/*
+ * arch/sh/drivers/pci/fixups-sh7785lcr.c
+ *
+ * R0P7785LC0011RL PCI fixups
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * Based on arch/sh/drivers/pci/fixups-r7780rp.c
+ * Copyright (C) 2003  Lineo uSolutions, Inc.
+ * Copyright (C) 2004 - 2006  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/pci.h>
+#include "pci-sh4.h"
+
+int pci_fixup_pcic(void)
+{
+	pci_write_reg(0x000043ff, SH4_PCIINTM);
+	pci_write_reg(0x0000380f, SH4_PCIAINTM);
+
+	pci_write_reg(0xfbb00047, SH7780_PCICMD);
+	pci_write_reg(0x00000000, SH7780_PCIIBAR);
+
+	pci_write_reg(0x00011912, SH7780_PCISVID);
+	pci_write_reg(0x08000000, SH7780_PCICSCR0);
+	pci_write_reg(0x0000001b, SH7780_PCICSAR0);
+	pci_write_reg(0xfd000000, SH7780_PCICSCR1);
+	pci_write_reg(0x0000000f, SH7780_PCICSAR1);
+
+	pci_write_reg(0xfd000000, SH7780_PCIMBR0);
+	pci_write_reg(0x00fc0000, SH7780_PCIMBMR0);
+
+#ifdef CONFIG_32BIT
+	pci_write_reg(0xc0000000, SH7780_PCIMBR2);
+	pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
+#endif
+
+	/* Set IOBR for windows containing area specified in pci.h */
+	pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),
+		      SH7780_PCIIOBR);
+	pci_write_reg(((SH7780_PCI_IO_SIZE - 1) & (7 << 18)), SH7780_PCIIOBMR);
+
+	return 0;
+}