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| author | Kevin Cernekee <cernekee@gmail.com> | 2014-10-20 21:28:00 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-11-24 07:45:12 +0100 |
| commit | d74b0172e4e2cea34104ba6bdacb3cffe33eaf0f (patch) | |
| tree | aca830adb2572cf37c1060c1b0ce4f9ac78700c0 /arch/sparc | |
| parent | d8010ceba66ac8d1953a1fb00ead89f4ee8a76f5 (diff) | |
| download | linux-d74b0172e4e2cea34104ba6bdacb3cffe33eaf0f.tar.gz linux-d74b0172e4e2cea34104ba6bdacb3cffe33eaf0f.tar.bz2 linux-d74b0172e4e2cea34104ba6bdacb3cffe33eaf0f.zip | |
MIPS: BMIPS: Add special cache handling in c-r4k.c
BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit,
so it isn't necessary to raise IPIs to keep both CPUs coherent.
BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$
fills from D$. But a special sequence with 2 SYNCs and 32 NOPs is needed
to ensure coherency.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8165/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/sparc')
0 files changed, 0 insertions, 0 deletions