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| author | Chris Metcalf <cmetcalf@tilera.com> | 2010-07-02 14:19:35 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2010-07-06 13:42:15 -0400 |
| commit | ef06f55a5c936a395f3ee2e1237bbebdb4396c65 (patch) | |
| tree | fce333d35dc147020a773ec36cfdb17690e2f00a /arch/tile/include/asm/cache.h | |
| parent | bcd97c3f9a385e8e658a416cd72dd65ca0eeb544 (diff) | |
| download | linux-ef06f55a5c936a395f3ee2e1237bbebdb4396c65.tar.gz linux-ef06f55a5c936a395f3ee2e1237bbebdb4396c65.tar.bz2 linux-ef06f55a5c936a395f3ee2e1237bbebdb4396c65.zip | |
arch/tile: catch up on various minor cleanups.
None of these changes fix any actual bugs, but are just various cleanups
that fell out along the way. In particular, some unused #defines and
includes are removed, PREFETCH_STRIDE is added (the default is right for
our shipping chips, but wrong for our next generation), our tile-specific
prefetching code is removed so the (identical) generic prefetching code
can be used instead, a comment is fixed to be proper GPL and not just a
"paste GPL here" token, a "//" comment is converted to "/* */", etc.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/tile/include/asm/cache.h')
| -rw-r--r-- | arch/tile/include/asm/cache.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index 869a14f4ceae..f6101840c9e7 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h @@ -21,11 +21,6 @@ #define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE() #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -/* bytes per L1 instruction cache line */ -#define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE() -#define L1I_CACHE_BYTES (1 << L1I_CACHE_SHIFT) -#define L1I_CACHE_ALIGN(x) (((x)+(L1I_CACHE_BYTES-1)) & -L1I_CACHE_BYTES) - /* bytes per L2 cache line */ #define L2_CACHE_SHIFT CHIP_L2_LOG_LINE_SIZE() #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) |