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| author | Chris Metcalf <cmetcalf@tilera.com> | 2013-09-03 14:41:36 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2013-09-03 14:47:34 -0400 |
| commit | acbde1db294932623aad15dd8cc6e37b28340f26 (patch) | |
| tree | 735ae530754f49ecfb006765463defdeea1167cd /arch/tile/kernel/head_64.S | |
| parent | 051168df528fe4456d63f5f65b041c147c26fe97 (diff) | |
| download | linux-acbde1db294932623aad15dd8cc6e37b28340f26.tar.gz linux-acbde1db294932623aad15dd8cc6e37b28340f26.tar.bz2 linux-acbde1db294932623aad15dd8cc6e37b28340f26.zip | |
tile: parameterize VA and PA space more cleanly
The existing code relied on the hardware definition (<arch/chip.h>)
to specify how much VA and PA space was available. It's convenient
to allow customizing this for some configurations, so provide symbols
MAX_PA_WIDTH and MAX_VA_WIDTH in <asm/page.h> that can be modified
if desired.
Additionally, move away from the MEM_XX_INTRPT nomenclature to
define the start of various regions within the VA space. In fact
the cleaner symbol is, for example, MEM_SV_START, to indicate the
start of the area used for supervisor code; the actual address of the
interrupt vectors is not as important, and can be changed if desired.
As part of this change, convert from "intrpt1" nomenclature (which
built in the old privilege-level 1 model) to a simple "intrpt".
Also strip out some tilepro-specific code supporting modifying the
PL the kernel could run at, since we don't actually support using
different PLs in tilepro, only tilegx.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/kernel/head_64.S')
| -rw-r--r-- | arch/tile/kernel/head_64.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/tile/kernel/head_64.S b/arch/tile/kernel/head_64.S index 652b81426158..bd0e12f283f3 100644 --- a/arch/tile/kernel/head_64.S +++ b/arch/tile/kernel/head_64.S @@ -135,9 +135,9 @@ ENTRY(_start) 1: /* Install the interrupt base. */ - moveli r0, hw2_last(MEM_SV_START) - shl16insli r0, r0, hw1(MEM_SV_START) - shl16insli r0, r0, hw0(MEM_SV_START) + moveli r0, hw2_last(intrpt_start) + shl16insli r0, r0, hw1(intrpt_start) + shl16insli r0, r0, hw0(intrpt_start) mtspr SPR_INTERRUPT_VECTOR_BASE_K, r0 /* Get our processor number and save it away in SAVE_K_0. */ |