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| author | Huang Ying <ying.huang@intel.com> | 2009-06-18 19:33:57 +0800 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2009-06-18 19:33:57 +0800 |
| commit | e6efaa025384f86a18814a6b9f4e5d54484ab9ff (patch) | |
| tree | e67688f905c8bbea2f35d4e001ef7790676a50e9 /arch/x86/crypto/aesni-intel_asm.S | |
| parent | 8d8409f773af2cfd52e23e4b138a7d55a31182cd (diff) | |
| download | linux-e6efaa025384f86a18814a6b9f4e5d54484ab9ff.tar.gz linux-e6efaa025384f86a18814a6b9f4e5d54484ab9ff.tar.bz2 linux-e6efaa025384f86a18814a6b9f4e5d54484ab9ff.zip | |
crypto: aes-ni - Fix cbc mode IV saving
Original implementation of aesni_cbc_dec do not save IV if input
length % 4 == 0. This will make decryption of next block failed.
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'arch/x86/crypto/aesni-intel_asm.S')
| -rw-r--r-- | arch/x86/crypto/aesni-intel_asm.S | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/x86/crypto/aesni-intel_asm.S b/arch/x86/crypto/aesni-intel_asm.S index caba99601703..eb0566e83319 100644 --- a/arch/x86/crypto/aesni-intel_asm.S +++ b/arch/x86/crypto/aesni-intel_asm.S @@ -845,7 +845,7 @@ ENTRY(aesni_cbc_enc) */ ENTRY(aesni_cbc_dec) cmp $16, LEN - jb .Lcbc_dec_ret + jb .Lcbc_dec_just_ret mov 480(KEYP), KLEN add $240, KEYP movups (IVP), IV @@ -891,6 +891,7 @@ ENTRY(aesni_cbc_dec) add $16, OUTP cmp $16, LEN jge .Lcbc_dec_loop1 - movups IV, (IVP) .Lcbc_dec_ret: + movups IV, (IVP) +.Lcbc_dec_just_ret: ret |