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authorBorislav Petkov <bp@suse.de>2020-08-20 11:10:15 +0200
committerBorislav Petkov <bp@suse.de>2020-08-24 10:23:40 +0200
commit0b2c605fa4ee3117c00b97b7af67791576b28f88 (patch)
treef9b6b5708f309aac92d8106ddd918662703cafce /arch/x86/entry/entry_64.S
parentd012a7190fc1fd72ed48911e77ca97ba4521bccd (diff)
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x86/entry/64: Correct the comment over SAVE_AND_SET_GSBASE
Add the proper explanation why an LFENCE is not needed in the FSGSBASE case. Fixes: c82965f9e530 ("x86/entry/64: Handle FSGSBASE enabled paranoid entry/exit") Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200821090710.GE12181@zn.tnic
Diffstat (limited to 'arch/x86/entry/entry_64.S')
-rw-r--r--arch/x86/entry/entry_64.S5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index 70dea9337816..bf78de4de7f0 100644
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -840,8 +840,9 @@ SYM_CODE_START_LOCAL(paranoid_entry)
* retrieve and set the current CPUs kernel GSBASE. The stored value
* has to be restored in paranoid_exit unconditionally.
*
- * The MSR write ensures that no subsequent load is based on a
- * mispredicted GSBASE. No extra FENCE required.
+ * The unconditional write to GS base below ensures that no subsequent
+ * loads based on a mispredicted GS base can happen, therefore no LFENCE
+ * is needed here.
*/
SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx
ret