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| author | Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> | 2017-02-24 02:48:15 -0600 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2017-03-30 09:53:52 +0200 |
| commit | dc6ca5e47d44c11a111807208595ff6a8fcd2a83 (patch) | |
| tree | ac669001322bb86dcf46ba5a35a1235f5a751f4c /arch/x86/events | |
| parent | 6aad0c6269052a6114259deaf664ce350bf64fa2 (diff) | |
| download | linux-dc6ca5e47d44c11a111807208595ff6a8fcd2a83.tar.gz linux-dc6ca5e47d44c11a111807208595ff6a8fcd2a83.tar.bz2 linux-dc6ca5e47d44c11a111807208595ff6a8fcd2a83.zip | |
x86/events/amd/iommu: Clean up perf_iommu_read()
Fix coding style and use GENMASK_ULL().
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Jörg Rödel <joro@8bytes.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: iommu@lists.linux-foundation.org
Link: http://lkml.kernel.org/r/1487926102-13073-4-git-send-email-Suravee.Suthikulpanit@amd.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/events')
| -rw-r--r-- | arch/x86/events/amd/iommu.c | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index e112f498a019..d4375dadd4e9 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -320,9 +320,7 @@ static void perf_iommu_start(struct perf_event *event, int flags) static void perf_iommu_read(struct perf_event *event) { - u64 count = 0ULL; - u64 prev_raw_count = 0ULL; - u64 delta = 0ULL; + u64 count, prev, delta; struct hw_perf_event *hwc = &event->hw; amd_iommu_pc_get_set_reg_val(_GET_DEVID(event), @@ -330,18 +328,16 @@ static void perf_iommu_read(struct perf_event *event) IOMMU_PC_COUNTER_REG, &count, false); /* IOMMU pc counter register is only 48 bits */ - count &= 0xFFFFFFFFFFFFULL; + count &= GENMASK_ULL(47, 0); - prev_raw_count = local64_read(&hwc->prev_count); - if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - count) != prev_raw_count) + prev = local64_read(&hwc->prev_count); + if (local64_cmpxchg(&hwc->prev_count, prev, count) != prev) return; - /* Handling 48-bit counter overflowing */ - delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT); + /* Handle 48-bit counter overflow */ + delta = (count << COUNTER_SHIFT) - (prev << COUNTER_SHIFT); delta >>= COUNTER_SHIFT; local64_add(delta, &event->count); - } static void perf_iommu_stop(struct perf_event *event, int flags) |