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| author | Dave Hansen <dave.hansen@linux.intel.com> | 2015-09-02 16:31:28 -0700 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2015-09-14 12:21:58 +0200 |
| commit | 8a93c9e0dca131a0bf330ea9d1e57c1bcf3824ad (patch) | |
| tree | a4fba9b4e589c29571882cf97f543ce452dccba5 /arch/x86/include/asm/fpu | |
| parent | dad8c4fe8530f28dde73dadd1d588e3aaa507562 (diff) | |
| download | linux-8a93c9e0dca131a0bf330ea9d1e57c1bcf3824ad.tar.gz linux-8a93c9e0dca131a0bf330ea9d1e57c1bcf3824ad.tar.bz2 linux-8a93c9e0dca131a0bf330ea9d1e57c1bcf3824ad.zip | |
x86/fpu: Rework XSTATE_* macros to remove magic '2'
The 'xstate.c' code has a bunch of references to '2'. This
is because we have a lot more work to do for the "extended"
xstates than the "legacy" ones and state component 2 is the
first "extended" state.
This patch replaces all of the instances of '2' with
FIRST_EXTENDED_XFEATURE, which clearly explains what is
going on.
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tim Chen <tim.c.chen@linux.intel.com>
Cc: dave@sr71.net
Cc: linux-kernel@vger.kernel.org
Link: http://lkml.kernel.org/r/20150902233128.A8C0BF51@viggo.jf.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/include/asm/fpu')
| -rw-r--r-- | arch/x86/include/asm/fpu/types.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/types.h index 8764df32f115..9f579305dd11 100644 --- a/arch/x86/include/asm/fpu/types.h +++ b/arch/x86/include/asm/fpu/types.h @@ -126,6 +126,8 @@ enum xfeature { | XFEATURE_MASK_ZMM_Hi256 \ | XFEATURE_MASK_Hi16_ZMM) +#define FIRST_EXTENDED_XFEATURE XFEATURE_YMM + /* * There are 16x 256-bit AVX registers named YMM0-YMM15. * The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15) |