diff options
| author | Andi Kleen <andi@firstfloor.org> | 2009-02-12 13:49:31 +0100 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2009-02-24 13:24:42 -0800 |
| commit | b276268631af3a1b0df871e10d19d492f0513d4b (patch) | |
| tree | 7646ccd6eb4987b02dcc777150d120b99069f8e0 /arch/x86/include/asm/mce.h | |
| parent | 41fdff322e26c4a86fe65cf577f2556a650cb7bc (diff) | |
| download | linux-b276268631af3a1b0df871e10d19d492f0513d4b.tar.gz linux-b276268631af3a1b0df871e10d19d492f0513d4b.tar.bz2 linux-b276268631af3a1b0df871e10d19d492f0513d4b.zip | |
x86, mce, cmci: factor out threshold interrupt handler
Impact: cleanup; preparation for feature
The mce_amd_64 code has an own private MC threshold vector with an own
interrupt handler. Since Intel needs a similar handler
it makes sense to share the vector because both can not
be active at the same time.
I factored the common APIC handler code into a separate file which can
be used by both the Intel or AMD MC code.
This is needed for the next patch which adds an Intel specific
CMCI handler.
This patch should be a nop for AMD, it just moves some code
around.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/mce.h')
| -rw-r--r-- | arch/x86/include/asm/mce.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 39136c497c5e..125cd8714622 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -135,5 +135,7 @@ extern void mcheck_init(struct cpuinfo_x86 *c); #define mcheck_init(c) do { } while (0) #endif +extern void (*mce_threshold_vector)(void); + #endif /* __KERNEL__ */ #endif /* _ASM_X86_MCE_H */ |