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| author | Rusty Russell <rusty@rustcorp.com.au> | 2009-09-24 09:34:51 -0600 |
|---|---|---|
| committer | Rusty Russell <rusty@rustcorp.com.au> | 2009-09-24 09:34:52 +0930 |
| commit | 78f1c4d6b027993763a5aba83873b0462d06db8f (patch) | |
| tree | d7a97d02e838b32c458c4ef23e9583d6faedc648 /arch/x86/include | |
| parent | fa40699b975131028a61aa8e095b0b17f350da40 (diff) | |
| download | linux-78f1c4d6b027993763a5aba83873b0462d06db8f.tar.gz linux-78f1c4d6b027993763a5aba83873b0462d06db8f.tar.bz2 linux-78f1c4d6b027993763a5aba83873b0462d06db8f.zip | |
cpumask: use mm_cpumask() wrapper: x86
Makes code futureproof against the impending change to mm->cpu_vm_mask (to be a pointer).
It's also a chance to use the new cpumask_ ops which take a pointer
(the older ones are deprecated, but there's no hurry for arch code).
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/mmu_context.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index f923203dc39a..4a2d4e0c18d9 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -37,12 +37,12 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, if (likely(prev != next)) { /* stop flush ipis for the previous mm */ - cpu_clear(cpu, prev->cpu_vm_mask); + cpumask_clear_cpu(cpu, mm_cpumask(prev)); #ifdef CONFIG_SMP percpu_write(cpu_tlbstate.state, TLBSTATE_OK); percpu_write(cpu_tlbstate.active_mm, next); #endif - cpu_set(cpu, next->cpu_vm_mask); + cpumask_set_cpu(cpu, mm_cpumask(next)); /* Re-load page tables */ load_cr3(next->pgd); @@ -58,7 +58,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, percpu_write(cpu_tlbstate.state, TLBSTATE_OK); BUG_ON(percpu_read(cpu_tlbstate.active_mm) != next); - if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) { + if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next))) { /* We were in lazy tlb mode and leave_mm disabled * tlb flush IPI delivery. We must reload CR3 * to make sure to use no freed page tables. |