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author | Sean Christopherson <sean.j.christopherson@intel.com> | 2019-12-20 20:44:58 -0800 |
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committer | Borislav Petkov <bp@suse.de> | 2020-01-13 17:45:45 +0100 |
commit | 1db2a6e1e29ff994443a9eef7cf3d26104c777a7 (patch) | |
tree | 19e5f1bc114340bf6ecb8bd5eee6e0c6575df2b2 /arch/x86/kernel/cpu/cpu.h | |
parent | f6505c88bff01e41b21a1f125edd1ace5330f164 (diff) | |
download | linux-1db2a6e1e29ff994443a9eef7cf3d26104c777a7.tar.gz linux-1db2a6e1e29ff994443a9eef7cf3d26104c777a7.tar.bz2 linux-1db2a6e1e29ff994443a9eef7cf3d26104c777a7.zip |
x86/intel: Initialize IA32_FEAT_CTL MSR at boot
Opportunistically initialize IA32_FEAT_CTL to enable VMX when the MSR is
left unlocked by BIOS. Configuring feature control at boot time paves
the way for similar enabling of other features, e.g. Software Guard
Extensions (SGX).
Temporarily leave equivalent KVM code in place in order to avoid
introducing a regression on Centaur and Zhaoxin CPUs, e.g. removing
KVM's code would leave the MSR unlocked on those CPUs and would break
existing functionality if people are loading kvm_intel on Centaur and/or
Zhaoxin. Defer enablement of the boot-time configuration on Centaur and
Zhaoxin to future patches to aid bisection.
Note, Local Machine Check Exceptions (LMCE) are also supported by the
kernel and enabled via feature control, but the kernel currently uses
LMCE if and only if the feature is explicitly enabled by BIOS. Keep
the current behavior to avoid introducing bugs, future patches can opt
in to opportunistic enabling if it's deemed desirable to do so.
Always lock IA32_FEAT_CTL if it exists, even if the CPU doesn't support
VMX, so that other existing and future kernel code that queries the MSR
can assume it's locked.
Start from a clean slate when constructing the value to write to
IA32_FEAT_CTL, i.e. ignore whatever value BIOS left in the MSR so as not
to enable random features or fault on the WRMSR.
Suggested-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20191221044513.21680-5-sean.j.christopherson@intel.com
Diffstat (limited to 'arch/x86/kernel/cpu/cpu.h')
-rw-r--r-- | arch/x86/kernel/cpu/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index 38ab6e115eac..37fdefd14f28 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -80,4 +80,8 @@ extern void x86_spec_ctrl_setup_ap(void); extern u64 x86_read_arch_cap_msr(void); +#ifdef CONFIG_IA32_FEAT_CTL +void init_ia32_feat_ctl(struct cpuinfo_x86 *c); +#endif + #endif /* ARCH_X86_CPU_H */ |