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| author | James Morris <james.l.morris@oracle.com> | 2014-10-01 00:44:04 +1000 |
|---|---|---|
| committer | James Morris <james.l.morris@oracle.com> | 2014-10-01 00:44:04 +1000 |
| commit | 6c8ff877cdf13cd5287ed9d700cfb6cb70e2bfa1 (patch) | |
| tree | 2ab49b7d19fb69cdae5b6be9e7ba44f6cf3d45ef /arch/x86/kernel/cpu/intel_cacheinfo.c | |
| parent | 35e1efd25a9e7d5cf2884fa23441ab87353849bb (diff) | |
| parent | 19583ca584d6f574384e17fe7613dfaeadcdc4a6 (diff) | |
| download | linux-6c8ff877cdf13cd5287ed9d700cfb6cb70e2bfa1.tar.gz linux-6c8ff877cdf13cd5287ed9d700cfb6cb70e2bfa1.tar.bz2 linux-6c8ff877cdf13cd5287ed9d700cfb6cb70e2bfa1.zip | |
Merge commit 'v3.16' into next
Diffstat (limited to 'arch/x86/kernel/cpu/intel_cacheinfo.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel_cacheinfo.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index a952e9c85b6f..9c8f7394c612 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -730,6 +730,18 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c) #endif } +#ifdef CONFIG_X86_HT + /* + * If cpu_llc_id is not yet set, this means cpuid_level < 4 which in + * turns means that the only possibility is SMT (as indicated in + * cpuid1). Since cpuid2 doesn't specify shared caches, and we know + * that SMT shares all caches, we can unconditionally set cpu_llc_id to + * c->phys_proc_id. + */ + if (per_cpu(cpu_llc_id, cpu) == BAD_APICID) + per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; +#endif + c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); return l2; |