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| author | Andi Kleen <andi@firstfloor.org> | 2009-07-09 00:31:44 +0200 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2009-07-09 18:39:47 -0700 |
| commit | a2d32bcbc008aa0f9c301a7c6f3494cb23e6af54 (patch) | |
| tree | ac4adb869a19d3cb0f67516b667a1f60e5c3cfa9 /arch/x86/kernel/cpu/mcheck/mce_intel.c | |
| parent | cebe182033f156b430952370fb0f9dbe6e89b081 (diff) | |
| download | linux-a2d32bcbc008aa0f9c301a7c6f3494cb23e6af54.tar.gz linux-a2d32bcbc008aa0f9c301a7c6f3494cb23e6af54.tar.bz2 linux-a2d32bcbc008aa0f9c301a7c6f3494cb23e6af54.zip | |
x86: mce: macros to compute banks MSRs
Instead of open coded calculations for bank MSRs hide the indexing of higher
banks MCE register MSRs in new macros.
No semantic changes.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/kernel/cpu/mcheck/mce_intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce_intel.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index e1acec0f7a32..889f665fe93d 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c @@ -90,7 +90,7 @@ static void cmci_discover(int banks, int boot) if (test_bit(i, owned)) continue; - rdmsrl(MSR_IA32_MC0_CTL2 + i, val); + rdmsrl(MSR_IA32_MCx_CTL2(i), val); /* Already owned by someone else? */ if (val & CMCI_EN) { @@ -101,8 +101,8 @@ static void cmci_discover(int banks, int boot) } val |= CMCI_EN | CMCI_THRESHOLD; - wrmsrl(MSR_IA32_MC0_CTL2 + i, val); - rdmsrl(MSR_IA32_MC0_CTL2 + i, val); + wrmsrl(MSR_IA32_MCx_CTL2(i), val); + rdmsrl(MSR_IA32_MCx_CTL2(i), val); /* Did the enable bit stick? -- the bank supports CMCI */ if (val & CMCI_EN) { @@ -152,9 +152,9 @@ void cmci_clear(void) if (!test_bit(i, __get_cpu_var(mce_banks_owned))) continue; /* Disable CMCI */ - rdmsrl(MSR_IA32_MC0_CTL2 + i, val); + rdmsrl(MSR_IA32_MCx_CTL2(i), val); val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK); - wrmsrl(MSR_IA32_MC0_CTL2 + i, val); + wrmsrl(MSR_IA32_MCx_CTL2(i), val); __clear_bit(i, __get_cpu_var(mce_banks_owned)); } spin_unlock_irqrestore(&cmci_discover_lock, flags); |