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| author | Thomas Gleixner <tglx@linutronix.de> | 2024-02-13 22:04:04 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2024-02-15 22:07:37 +0100 |
| commit | 598e719c40d67b1473d78423e941bed4ea6c726d (patch) | |
| tree | deef1ceb0f8a8417250fd72fd210f0706f757a90 /arch/x86/kernel/cpu/zhaoxin.c | |
| parent | bda74aae20086c044b31ca0dcdab7deaaf23d0e8 (diff) | |
| download | linux-598e719c40d67b1473d78423e941bed4ea6c726d.tar.gz linux-598e719c40d67b1473d78423e941bed4ea6c726d.tar.bz2 linux-598e719c40d67b1473d78423e941bed4ea6c726d.zip | |
x86/cpu: Use common topology code for Centaur and Zhaoxin
Centaur and Zhaoxin CPUs use only the legacy SMP detection. Remove the
invocations from their 32bit path and exclude them from the 64-bit call
path.
No functional change intended.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Tested-by: Sohil Mehta <sohil.mehta@intel.com>
Tested-by: Michael Kelley <mhklinux@outlook.com>
Tested-by: Zhang Rui <rui.zhang@intel.com>
Tested-by: Wang Wendy <wendy.wang@intel.com>
Tested-by: K Prateek Nayak <kprateek.nayak@amd.com>
Link: https://lore.kernel.org/r/20240212153624.706794189@linutronix.de
Diffstat (limited to 'arch/x86/kernel/cpu/zhaoxin.c')
| -rw-r--r-- | arch/x86/kernel/cpu/zhaoxin.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index 415564a6523b..90eba7eb5335 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -71,10 +71,6 @@ static void init_zhaoxin(struct cpuinfo_x86 *c) { early_init_zhaoxin(c); init_intel_cacheinfo(c); - detect_num_cpu_cores(c); -#ifdef CONFIG_X86_32 - detect_ht(c); -#endif if (c->cpuid_level > 9) { unsigned int eax = cpuid_eax(10); |