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author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2016-09-08 13:32:31 +0300 |
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committer | Ingo Molnar <mingo@kernel.org> | 2016-09-08 14:07:53 +0200 |
commit | 8e522e1d321b12829960c9b26668c92f14c68d7f (patch) | |
tree | 8774a3d995d9eba39c40e7ab299c85a1a8908e46 /arch/x86/platform/intel-mid/pwr.c | |
parent | f5fbf848303c8704d0e1a1e7cabd08fd0a49552f (diff) | |
download | linux-8e522e1d321b12829960c9b26668c92f14c68d7f.tar.gz linux-8e522e1d321b12829960c9b26668c92f14c68d7f.tar.bz2 linux-8e522e1d321b12829960c9b26668c92f14c68d7f.zip |
x86/platform/intel-mid: Add Intel Penwell to ID table
Commit:
ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")
... enabled the PWRMU driver on platforms based on Intel Penwell, but
unfortunately this is not enough.
Add Intel Penwell ID to pci-mid.c driver as well. To avoid confusion in the
future add a comment to both drivers.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Fixes: ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")
Link: http://lkml.kernel.org/r/20160908103232.137587-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/platform/intel-mid/pwr.c')
-rw-r--r-- | arch/x86/platform/intel-mid/pwr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c index 2dfe998a5afd..146ed54e92e5 100644 --- a/arch/x86/platform/intel-mid/pwr.c +++ b/arch/x86/platform/intel-mid/pwr.c @@ -427,6 +427,7 @@ static const struct mid_pwr_device_info mid_info = { .set_initial_state = mid_set_initial_state, }; +/* This table should be in sync with the one in drivers/pci/pci-mid.c */ static const struct pci_device_id mid_pwr_pci_ids[] = { { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info }, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info }, |