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| author | Suresh Siddha <suresh.b.siddha@intel.com> | 2008-08-27 14:57:36 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2008-08-27 15:23:23 -0700 |
| commit | 83b8e28b14d63db928cb39e5c5ed2a548246bd71 (patch) | |
| tree | 27abd5df0e150e411265ac5a2c834279813eb8dc /arch/x86 | |
| parent | f65bc214e042916135256620f900e9599d65e0cb (diff) | |
| download | linux-83b8e28b14d63db928cb39e5c5ed2a548246bd71.tar.gz linux-83b8e28b14d63db928cb39e5c5ed2a548246bd71.tar.bz2 linux-83b8e28b14d63db928cb39e5c5ed2a548246bd71.zip | |
x86: xsave: restore xcr0 during resume
Add the missing XCR0(XFEATURE_ENABLED_MASK) restore during resume.
Reported-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/power/cpu_32.c | 7 | ||||
| -rw-r--r-- | arch/x86/power/cpu_64.c | 7 |
2 files changed, 14 insertions, 0 deletions
diff --git a/arch/x86/power/cpu_32.c b/arch/x86/power/cpu_32.c index 7dc5d5cf50a2..02f36f53558c 100644 --- a/arch/x86/power/cpu_32.c +++ b/arch/x86/power/cpu_32.c @@ -11,6 +11,7 @@ #include <linux/suspend.h> #include <asm/mtrr.h> #include <asm/mce.h> +#include <asm/xcr.h> static struct saved_context saved_context; @@ -124,6 +125,12 @@ static void __restore_processor_state(struct saved_context *ctxt) if (boot_cpu_has(X86_FEATURE_SEP)) enable_sep_cpu(); + /* + * restore XCR0 for xsave capable cpu's. + */ + if (cpu_has_xsave) + xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask); + fix_processor_context(); do_fpu_end(); mtrr_ap_init(); diff --git a/arch/x86/power/cpu_64.c b/arch/x86/power/cpu_64.c index 66bdfb591fd8..e3b6cf70d62c 100644 --- a/arch/x86/power/cpu_64.c +++ b/arch/x86/power/cpu_64.c @@ -14,6 +14,7 @@ #include <asm/page.h> #include <asm/pgtable.h> #include <asm/mtrr.h> +#include <asm/xcr.h> static void fix_processor_context(void); @@ -122,6 +123,12 @@ static void __restore_processor_state(struct saved_context *ctxt) wrmsrl(MSR_GS_BASE, ctxt->gs_base); wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); + /* + * restore XCR0 for xsave capable cpu's. + */ + if (cpu_has_xsave) + xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask); + fix_processor_context(); do_fpu_end(); |