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authorJoerg Roedel <joerg.roedel@amd.com>2010-07-27 17:14:24 +0200
committerJoerg Roedel <joerg.roedel@amd.com>2010-07-27 17:14:24 +0200
commit80a506b8fdcfa868bb53eb740f928217d0966fc1 (patch)
tree07efb59ecb6050712262387aa2fe3b952743fda5 /arch/x86
parent6c54aabd5e687092557f4881ce2d4013b971f293 (diff)
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x86/amd-iommu: Export cache-coherency capability
This patch exports the capability of the AMD IOMMU to force cache coherency of DMA transactions through the IOMMU-API. This is required to disable some nasty hacks in KVM when this capability is not available. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/kernel/amd_iommu.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index 29dd3b9f2f09..fa044e1e30a2 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -2572,6 +2572,11 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
unsigned long cap)
{
+ switch (cap) {
+ case IOMMU_CAP_CACHE_COHERENCY:
+ return 1;
+ }
+
return 0;
}