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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-05-11 10:27:34 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-05-11 10:27:34 -0400 |
| commit | 7a5575212ce4b6a41581b92fe03b6be1134793ba (patch) | |
| tree | f76ae29af196387330dd9a7c4a86200cbe80182c /arch/xtensa/Kconfig | |
| parent | 1fb3b526df3bd7647e7854915ae6b22299408baf (diff) | |
| parent | a5944195d00a359e28d6e093593609bcee37ed5e (diff) | |
| download | linux-7a5575212ce4b6a41581b92fe03b6be1134793ba.tar.gz linux-7a5575212ce4b6a41581b92fe03b6be1134793ba.tar.bz2 linux-7a5575212ce4b6a41581b92fe03b6be1134793ba.zip | |
Merge tag 'xtensa-20190510' of git://github.com/jcmvbkbc/linux-xtensa
Pull xtensa updates from Max Filippov:
- implement atomic operations using exclusive access Xtensa option
operations
- add support for Xtensa cores with memory protection unit (MPU)
- clean up xtensa-specific kernel-only headers
- fix error path in simdisk_setup
* tag 'xtensa-20190510' of git://github.com/jcmvbkbc/linux-xtensa:
xtensa: implement initialize_cacheattr for MPU cores
xtensa: add exclusive atomics support
xtensa: clean up inline assembly in futex.h
xtensa: replace variant/core.h with asm/core.h
xtensa: drop ifdef __KERNEL__ from kernel-only headers
xtensa: set proper error code for simdisk_setup()
xtensa: fix incorrect fd close in error case of simdisk_setup()
Diffstat (limited to 'arch/xtensa/Kconfig')
| -rw-r--r-- | arch/xtensa/Kconfig | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 35c8d91e6106..6ec1b75eabc5 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -253,12 +253,26 @@ config MEMMAP_CACHEATTR region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. - Cache attribute values are specific for the MMU type, so e.g. - for region protection MMUs: 2 is cache bypass, 4 is WB cached, - 1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable, - bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass, - 1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is - reserved). + Cache attribute values are specific for the MMU type. + For region protection MMUs: + 1: WT cached, + 2: cache bypass, + 4: WB cached, + f: illegal. + For ful MMU: + bit 0: executable, + bit 1: writable, + bits 2..3: + 0: cache bypass, + 1: WB cache, + 2: WT cache, + 3: special (c and e are illegal, f is reserved). + For MPU: + 0: illegal, + 1: WB cache, + 2: WB, no-write-allocate cache, + 3: WT cache, + 4: cache bypass. config KSEG_PADDR hex "Physical address of the KSEG mapping" |