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| author | Mike Frysinger <vapier.adi@gmail.com> | 2009-01-07 23:14:38 +0800 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2009-01-07 23:14:38 +0800 |
| commit | 94106e0fb6b863348a566617ca6bf431c37ddc5e (patch) | |
| tree | 93b1598d677c6df18fdf1e95c58847c66438b482 /arch | |
| parent | 1ea9925553caad6ea5068b4652596f149e0be9c3 (diff) | |
| download | linux-94106e0fb6b863348a566617ca6bf431c37ddc5e.tar.gz linux-94106e0fb6b863348a566617ca6bf431c37ddc5e.tar.bz2 linux-94106e0fb6b863348a566617ca6bf431c37ddc5e.zip | |
Blackfin arch: do not allow L2 to be cached on BF561 SMP
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/blackfin/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index b8bc5a402fa4..f8edfbe5faed 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -866,7 +866,7 @@ endchoice config BFIN_L2_CACHEABLE bool "Cache L2 SRAM" - depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561) + depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP)) default n help Select to make L2 SRAM cacheable in L1 data and instruction cache. |