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| author | Dan Williams <dan.j.williams@intel.com> | 2008-10-24 10:21:45 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2008-10-24 10:21:45 -0700 |
| commit | 6bee00dbbcb1e9feb0510e9a7104b4af00adc574 (patch) | |
| tree | dd0b20bbbe353ece29a78a75b155e6d8bbd2c86e /arch | |
| parent | e013e13bf605b9e6b702adffbe2853cfc60e7806 (diff) | |
| download | linux-6bee00dbbcb1e9feb0510e9a7104b4af00adc574.tar.gz linux-6bee00dbbcb1e9feb0510e9a7104b4af00adc574.tar.bz2 linux-6bee00dbbcb1e9feb0510e9a7104b4af00adc574.zip | |
[ARM] xsc3: revert writethrough memory-type encoding change
Commit 40df2d1d "[ARM] Update Xscale and Xscale3 PTE mappings" was
fingered by git-bisect for a boot failure on iop13xx. The change made
L_PTE_MT_WRITETHROUGH mappings L2-uncacheable. Russell points out that
this mapping is used for the vector page. Given the regression, and the
fact this page is used often, restore the old behaviour.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mm/proc-xsc3.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 04dc8b65401b..8f6cf56c11c0 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -349,7 +349,7 @@ ENTRY(cpu_xsc3_switch_mm) cpu_xsc3_mt_table: .long 0x00 @ L_PTE_MT_UNCACHED .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE - .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH + .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED .long 0x00 @ unused |