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| author | Rajendra Nayak <rnayak@ti.com> | 2009-07-24 19:44:02 -0600 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-07-24 20:10:35 -0600 |
| commit | df56556e571234cf26072cd58c01ac3520986b44 (patch) | |
| tree | 6160ddc198741c1f759f966185a81aceae5966ca /arch | |
| parent | 8ff120e5303e27e03aba7b774e86fd43eaf90376 (diff) | |
| download | linux-df56556e571234cf26072cd58c01ac3520986b44.tar.gz linux-df56556e571234cf26072cd58c01ac3520986b44.tar.bz2 linux-df56556e571234cf26072cd58c01ac3520986b44.zip | |
OMAP3 SDRC: Move the clk stabilization delay to the right place
The clock stabilization delay post a M2 divider change is needed
even before a SDRC interface clock re-enable and not only before
jumping back to SDRAM.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/sram34xx.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index e6b112590d7d..82aa4a3d160c 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -127,6 +127,8 @@ skip_cs1_params: blne lock_dll bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC bl configure_core_dpll @ change the DPLL3 M2 divider + mov r12, r2 + bl wait_clk_stable @ wait for SDRC to stabilize bl enable_sdrc @ take SDRC out of idle cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change bleq wait_dll_unlock @@ -134,8 +136,6 @@ skip_cs1_params: cmp r3, #1 @ if increasing SDRC clk rate, beq return_to_sdram @ return to SDRAM code, otherwise, bl configure_sdrc @ reprogram SDRC regs now - mov r12, r2 - bl wait_clk_stable @ wait for SDRC to stabilize return_to_sdram: isb @ prevent speculative exec past here mov r0, #0 @ return value |