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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-06-03 10:43:13 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-04-27 14:15:23 +1000 |
| commit | a7ede1abeefd69330c5dd45b335d22af1e2baf2e (patch) | |
| tree | a699d2b6b736ad3b8284332871b0025f83b6224a /arch | |
| parent | 8574de861978d5187da4f2b7dcf127a5795e967f (diff) | |
| download | linux-a7ede1abeefd69330c5dd45b335d22af1e2baf2e.tar.gz linux-a7ede1abeefd69330c5dd45b335d22af1e2baf2e.tar.bz2 linux-a7ede1abeefd69330c5dd45b335d22af1e2baf2e.zip | |
ARM: dts: r8a7793: Add SYSC PM Domains
Add a device node for the System Controller.
Hook up the first Cortex-A15 CPU core and the Cortex-A15 L2 cache/SCU to
their respective PM Domains.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/r8a7793.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 6186179fd66d..53e235e3279d 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/clock/r8a7793-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/power/r8a7793-sysc.h> / { compatible = "renesas,r8a7793"; @@ -43,6 +44,7 @@ voltage-tolerance = <1>; /* 1% */ clocks = <&cpg_clocks R8A7793_CLK_Z>; clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7793_PD_CA15_CPU0>; /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -76,6 +78,7 @@ L2_CA15: cache-controller@0 { compatible = "cache"; + power-domains = <&sysc R8A7793_PD_CA15_SCU>; cache-unified; cache-level = <2>; }; @@ -1223,6 +1226,12 @@ }; }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7793-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + ipmmu_sy0: mmu@e6280000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; |