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author | David Carrillo-Cisneros <davidcc@google.com> | 2016-06-21 11:31:13 -0700 |
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committer | Ingo Molnar <mingo@kernel.org> | 2016-06-27 11:34:20 +0200 |
commit | 71adae99ed187de9fcf988cc8873ee2c3af3385f (patch) | |
tree | a7904984a9867ad248a2dadd5ecb0f16ed6c8a85 /arch | |
parent | 3812bba84f3d721ff7dc3bb90360bc5ed6771994 (diff) | |
download | linux-71adae99ed187de9fcf988cc8873ee2c3af3385f.tar.gz linux-71adae99ed187de9fcf988cc8873ee2c3af3385f.tar.bz2 linux-71adae99ed187de9fcf988cc8873ee2c3af3385f.zip |
perf/x86/intel: Add MSR_LAST_BRANCH_FROM_x quirk for ctx switch
Add quirk for context switch to save/restore the value of
MSR_LAST_BRANCH_FROM_x when LBR is enabled and there is potential for
kernel addresses to be in the lbr_from register.
To test this patch, use a perf tool and kernel with the patch
next in this series. That patch removes the work around that masked
the hw bug:
$ ./lbr_perf record --call-graph lbr -e cycles:k sleep 1
where lbr_perf is the patched perf tool, that allows to specify :k
on lbr mode. The above command will trigger a #GPF :
WARNING: CPU: 28 PID: 14096 at arch/x86/mm/extable.c:65 ex_handler_wrmsr_unsafe+0x70/0x80
unchecked MSR access error: WRMSR to 0x681 (tried to write 0x1fffffff81010794)
...
Call Trace:
[<ffffffff8167af49>] dump_stack+0x4d/0x63
[<ffffffff810b9b15>] __warn+0xe5/0x100
[<ffffffff810b9be9>] warn_slowpath_fmt+0x49/0x50
[<ffffffff810abb40>] ex_handler_wrmsr_unsafe+0x70/0x80
[<ffffffff810abc42>] fixup_exception+0x42/0x50
[<ffffffff81079d1a>] do_general_protection+0x8a/0x160
[<ffffffff81684ec2>] general_protection+0x22/0x30
[<ffffffff810101b9>] ? intel_pmu_lbr_sched_task+0xc9/0x380
[<ffffffff81009d7c>] intel_pmu_sched_task+0x3c/0x60
[<ffffffff81003a2b>] x86_pmu_sched_task+0x1b/0x20
[<ffffffff81192a5b>] perf_pmu_sched_task+0x6b/0xb0
[<ffffffff8119746d>] __perf_event_task_sched_in+0x7d/0x150
[<ffffffff810dd9dc>] finish_task_switch+0x15c/0x200
[<ffffffff8167f894>] __schedule+0x274/0x6cc
[<ffffffff8167fdd9>] schedule+0x39/0x90
[<ffffffff81675398>] exit_to_usermode_loop+0x39/0x89
[<ffffffff810028ce>] prepare_exit_to_usermode+0x2e/0x30
[<ffffffff81683c1b>] retint_user+0x8/0x10
Signed-off-by: David Carrillo-Cisneros <davidcc@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Stephane Eranian <eranian@google.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1466533874-52003-5-git-send-email-davidcc@google.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/x86/events/intel/lbr.c | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 0da0eb0d875d..52bef15c7615 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -284,6 +284,20 @@ inline u64 lbr_from_signext_quirk_wr(u64 val) return val; } +/* + * If quirk is needed, ensure sign extension is 61 bits: + */ +u64 lbr_from_signext_quirk_rd(u64 val) +{ + if (static_branch_unlikely(&lbr_from_quirk_key)) + /* + * Quirk is on when TSX is not enabled. Therefore TSX + * flags must be read as OFF. + */ + val &= ~(LBR_FROM_FLAG_IN_TX | LBR_FROM_FLAG_ABORT); + return val; +} + static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx) { int i; @@ -300,7 +314,8 @@ static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx) tos = task_ctx->tos; for (i = 0; i < tos; i++) { lbr_idx = (tos - i) & mask; - wrmsrl(x86_pmu.lbr_from + lbr_idx, task_ctx->lbr_from[i]); + wrmsrl(x86_pmu.lbr_from + lbr_idx, + lbr_from_signext_quirk_wr(task_ctx->lbr_from[i])); wrmsrl(x86_pmu.lbr_to + lbr_idx, task_ctx->lbr_to[i]); if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) wrmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]); @@ -313,7 +328,7 @@ static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx) { int i; unsigned lbr_idx, mask; - u64 tos; + u64 tos, val; if (task_ctx->lbr_callstack_users == 0) { task_ctx->lbr_stack_state = LBR_NONE; @@ -324,7 +339,8 @@ static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx) tos = intel_pmu_lbr_tos(); for (i = 0; i < tos; i++) { lbr_idx = (tos - i) & mask; - rdmsrl(x86_pmu.lbr_from + lbr_idx, task_ctx->lbr_from[i]); + rdmsrl(x86_pmu.lbr_from + lbr_idx, val); + task_ctx->lbr_from[i] = lbr_from_signext_quirk_rd(val); rdmsrl(x86_pmu.lbr_to + lbr_idx, task_ctx->lbr_to[i]); if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]); @@ -502,6 +518,8 @@ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc) int lbr_flags = lbr_desc[lbr_format]; rdmsrl(x86_pmu.lbr_from + lbr_idx, from); + from = lbr_from_signext_quirk_rd(from); + rdmsrl(x86_pmu.lbr_to + lbr_idx, to); if (lbr_format == LBR_FORMAT_INFO && need_info) { |