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authorAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>2015-12-01 09:06:47 +0530
committerMichael Ellerman <mpe@ellerman.id.au>2015-12-14 15:19:11 +1100
commit227fdbee5a963f4358bb1edd78a6f654574a4991 (patch)
tree80e02c0c603b5795dd754a91970d33b6ef8d564b /arch
parent506b863c68cd6e720037f1548e101932af3bb006 (diff)
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powerpc/mm: Increase the width of #define
No real change, only style changes Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/book3s/64/hash.h26
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index 2f2034621a69..e4ea9d73a541 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -69,23 +69,23 @@
* We could create separate kernel read-only if we used the 3 PP bits
* combinations that newer processors provide but we currently don't.
*/
-#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
-#define _PAGE_USER 0x0002 /* matches one of the PP bits */
+#define _PAGE_PRESENT 0x00001 /* software: pte contains a translation */
+#define _PAGE_USER 0x00002 /* matches one of the PP bits */
#define _PAGE_BIT_SWAP_TYPE 2
-#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
-#define _PAGE_GUARDED 0x0008
+#define _PAGE_EXEC 0x00004 /* No execute on POWER4 and newer (we invert) */
+#define _PAGE_GUARDED 0x00008
/* We can derive Memory coherence from _PAGE_NO_CACHE */
#define _PAGE_COHERENT 0x0
-#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
-#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
-#define _PAGE_DIRTY 0x0080 /* C: page changed */
-#define _PAGE_ACCESSED 0x0100 /* R: page referenced */
-#define _PAGE_RW 0x0200 /* software: user write access allowed */
-#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
-#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
-#define _PAGE_F_GIX 0x7000 /* full page: hidx bits */
+#define _PAGE_NO_CACHE 0x00020 /* I: cache inhibit */
+#define _PAGE_WRITETHRU 0x00040 /* W: cache write-through */
+#define _PAGE_DIRTY 0x00080 /* C: page changed */
+#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
+#define _PAGE_RW 0x00200 /* software: user write access allowed */
+#define _PAGE_HASHPTE 0x00400 /* software: pte has an associated HPTE */
+#define _PAGE_BUSY 0x00800 /* software: PTE & hash are busy */
+#define _PAGE_F_GIX 0x07000 /* full page: hidx bits */
#define _PAGE_F_GIX_SHIFT 12
-#define _PAGE_F_SECOND 0x8000 /* Whether to use secondary hash or not */
+#define _PAGE_F_SECOND 0x08000 /* Whether to use secondary hash or not */
#define _PAGE_SPECIAL 0x10000 /* software: special page */
/* No separate kernel read-only */