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| author | Jonathan Hunter <jonathanh@nvidia.com> | 2019-05-02 14:27:21 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-05-08 14:42:51 +0200 |
| commit | dfdbf16c50d89a8cb102a5f7a1f53686fff506ad (patch) | |
| tree | 6cbcbdf6b16b7d00a4650ef555d1c0da1631c447 /arch | |
| parent | 2f03e39b5bfe41f3a0d9a8b01231e7e5045cb9c4 (diff) | |
| download | linux-dfdbf16c50d89a8cb102a5f7a1f53686fff506ad.tar.gz linux-dfdbf16c50d89a8cb102a5f7a1f53686fff506ad.tar.bz2 linux-dfdbf16c50d89a8cb102a5f7a1f53686fff506ad.zip | |
arm64: tegra: Fix insecure SMMU users for Tegra186
Commit 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling
bypass by default") intentionally breaks all devices using the SMMU in
bypass mode. This is breaking various devices on Tegra186 which include
the ethernet, BPMP and HDA device. Fix this by populating the iommus
property for these devices with their stream ID.
Fixes: 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling bypass by default")
Signed-off-by: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra186.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index f0bb6ced4976..3fb60f6f3a93 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -60,6 +60,7 @@ clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; resets = <&bpmp TEGRA186_RESET_EQOS>; reset-names = "eqos"; + iommus = <&smmu TEGRA186_SID_EQOS>; status = "disabled"; snps,write-requests = <1>; @@ -338,6 +339,7 @@ <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; reset-names = "hda", "hda2hdmi", "hda2codec_2x"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; + iommus = <&smmu TEGRA186_SID_HDA>; status = "disabled"; }; @@ -1158,6 +1160,7 @@ bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; + iommus = <&smmu TEGRA186_SID_BPMP>; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; |