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author | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2018-03-20 14:07:59 +0100 |
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committer | James Hogan <jhogan@kernel.org> | 2018-03-21 23:33:00 +0000 |
commit | 6b36d31a8a997248a10059e6d8a4e31b9c8310a2 (patch) | |
tree | a9a39090cae7d341702ef43136a40f64756e3855 /arch | |
parent | d843dd530d57e75a9fd1bfd694bd1f13eb5fe8d4 (diff) | |
download | linux-6b36d31a8a997248a10059e6d8a4e31b9c8310a2.tar.gz linux-6b36d31a8a997248a10059e6d8a4e31b9c8310a2.tar.bz2 linux-6b36d31a8a997248a10059e6d8a4e31b9c8310a2.zip |
MIPS: mscc: Add ocelot PCB123 device tree
Add a device tree for the Microsemi Ocelot PCB123 evaluation board.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Allan Nielsen <Allan.Nielsen@microsemi.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/18856/
Signed-off-by: James Hogan <jhogan@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/boot/dts/mscc/Makefile | 2 | ||||
-rw-r--r-- | arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 27 |
2 files changed, 29 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile index dd08e63a10ba..c51164537c02 100644 --- a/arch/mips/boot/dts/mscc/Makefile +++ b/arch/mips/boot/dts/mscc/Makefile @@ -1 +1,3 @@ +dtb-$(CONFIG_LEGACY_BOARD_OCELOT) += ocelot_pcb123.dtb + obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts new file mode 100644 index 000000000000..29d6414f8886 --- /dev/null +++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2017 Microsemi Corporation */ + +/dts-v1/; + +#include "ocelot.dtsi" + +/ { + compatible = "mscc,ocelot-pcb123", "mscc,ocelot"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0e000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; |