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authorRyder Lee <ryder.lee@mediatek.com>2017-10-20 17:46:46 +0800
committerMatthias Brugger <matthias.bgg@gmail.com>2017-11-02 19:43:19 +0100
commite4316d6f2ccdeb2776d13651d32a6107cced274c (patch)
treee20b8d2b2800778cb8ecdadd829f53e05a5d2a36 /arch
parenta336ba44feb2b022872987e97125e3283d07bfc2 (diff)
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arm: dts: mt7623: update usb related nodes
The current usb related nodes are out-of-date, so we make them be consistent with the binding documents. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/mt7623.dtsi16
1 files changed, 10 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 01071cc78046..031f4463b14d 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -680,7 +680,7 @@
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
<&topckgen CLK_TOP_ETHIF_SEL>;
- clock-names = "sys_ck", "free_ck";
+ clock-names = "sys_ck", "ref_ck";
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
status = "disabled";
@@ -690,8 +690,6 @@
compatible = "mediatek,mt7623-u3phy",
"mediatek,mt2701-u3phy";
reg = <0 0x1a1c4000 0 0x0700>;
- clocks = <&clk26m>;
- clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -699,12 +697,16 @@
u2port0: usb-phy@1a1c4800 {
reg = <0 0x1a1c4800 0 0x0100>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u3port0: usb-phy@1a1c4900 {
reg = <0 0x1a1c4900 0 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
@@ -719,7 +721,7 @@
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
<&topckgen CLK_TOP_ETHIF_SEL>;
- clock-names = "sys_ck", "free_ck";
+ clock-names = "sys_ck", "ref_ck";
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
status = "disabled";
@@ -729,8 +731,6 @@
compatible = "mediatek,mt7623-u3phy",
"mediatek,mt2701-u3phy";
reg = <0 0x1a244000 0 0x0700>;
- clocks = <&clk26m>;
- clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -738,12 +738,16 @@
u2port1: usb-phy@1a244800 {
reg = <0 0x1a244800 0 0x0100>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
u3port1: usb-phy@1a244900 {
reg = <0 0x1a244900 0 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};