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author | Hauke Mehrtens <hauke.mehrtens@lantiq.com> | 2015-10-28 23:37:38 +0100 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2015-11-11 08:37:18 +0100 |
commit | eefee024b012df827fd0aebffcd05665d8511a8a (patch) | |
tree | 6587a07ff2a1a22ae6667ad903a05d8fcb50da63 /arch | |
parent | d0b991e376e6293f1122813f28c63d3c93fdc97b (diff) | |
download | linux-eefee024b012df827fd0aebffcd05665d8511a8a.tar.gz linux-eefee024b012df827fd0aebffcd05665d8511a8a.tar.bz2 linux-eefee024b012df827fd0aebffcd05665d8511a8a.zip |
MIPS: Lantiq: Add support for gphy firmware loading for ar10 and grx390
Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11389/
Patchwork: https://patchwork.linux-mips.org/patch/11398/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/lantiq/xway/reset.c | 112 |
1 files changed, 92 insertions, 20 deletions
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c index fe68f9ae47c1..12a7d824d0b6 100644 --- a/arch/mips/lantiq/xway/reset.c +++ b/arch/mips/lantiq/xway/reset.c @@ -4,6 +4,7 @@ * by the Free Software Foundation. * * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG */ #include <linux/init.h> @@ -22,9 +23,6 @@ #include "../prom.h" -#define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y)) -#define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x)) - /* reset request register */ #define RCU_RST_REQ 0x0010 /* reset status register */ @@ -32,11 +30,29 @@ /* vr9 gphy registers */ #define RCU_GFS_ADD0_XRX200 0x0020 #define RCU_GFS_ADD1_XRX200 0x0068 +/* xRX300 gphy registers */ +#define RCU_GFS_ADD0_XRX300 0x0020 +#define RCU_GFS_ADD1_XRX300 0x0058 +#define RCU_GFS_ADD2_XRX300 0x00AC +/* xRX330 gphy registers */ +#define RCU_GFS_ADD0_XRX330 0x0020 +#define RCU_GFS_ADD1_XRX330 0x0058 +#define RCU_GFS_ADD2_XRX330 0x00AC +#define RCU_GFS_ADD3_XRX330 0x0264 /* reboot bit */ #define RCU_RD_GPHY0_XRX200 BIT(31) #define RCU_RD_SRST BIT(30) #define RCU_RD_GPHY1_XRX200 BIT(29) +/* xRX300 bits */ +#define RCU_RD_GPHY0_XRX300 BIT(31) +#define RCU_RD_GPHY1_XRX300 BIT(29) +#define RCU_RD_GPHY2_XRX300 BIT(28) +/* xRX330 bits */ +#define RCU_RD_GPHY0_XRX330 BIT(31) +#define RCU_RD_GPHY1_XRX330 BIT(29) +#define RCU_RD_GPHY2_XRX330 BIT(28) +#define RCU_RD_GPHY3_XRX330 BIT(10) /* reset cause */ #define RCU_STAT_SHIFT 26 @@ -47,6 +63,26 @@ /* remapped base addr of the reset control unit */ static void __iomem *ltq_rcu_membase; static struct device_node *ltq_rcu_np; +static DEFINE_SPINLOCK(ltq_rcu_lock); + +static void ltq_rcu_w32(uint32_t val, uint32_t reg_off) +{ + ltq_w32(val, ltq_rcu_membase + reg_off); +} + +static uint32_t ltq_rcu_r32(uint32_t reg_off) +{ + return ltq_r32(ltq_rcu_membase + reg_off); +} + +static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off) +{ + unsigned long flags; + + spin_lock_irqsave(<q_rcu_lock, flags); + ltq_rcu_w32((ltq_rcu_r32(reg_off) & ~(clr)) | (set), reg_off); + spin_unlock_irqrestore(<q_rcu_lock, flags); +} /* This function is used by the watchdog driver */ int ltq_reset_cause(void) @@ -67,15 +103,40 @@ unsigned char ltq_boot_select(void) return RCU_BOOT_SEL(val); } -/* reset / boot a gphy */ -static struct ltq_xrx200_gphy_reset { +struct ltq_gphy_reset { u32 rd; u32 addr; -} xrx200_gphy[] = { +}; + +/* reset / boot a gphy */ +static struct ltq_gphy_reset xrx200_gphy[] = { {RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200}, {RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200}, }; +/* reset / boot a gphy */ +static struct ltq_gphy_reset xrx300_gphy[] = { + {RCU_RD_GPHY0_XRX300, RCU_GFS_ADD0_XRX300}, + {RCU_RD_GPHY1_XRX300, RCU_GFS_ADD1_XRX300}, + {RCU_RD_GPHY2_XRX300, RCU_GFS_ADD2_XRX300}, +}; + +/* reset / boot a gphy */ +static struct ltq_gphy_reset xrx330_gphy[] = { + {RCU_RD_GPHY0_XRX330, RCU_GFS_ADD0_XRX330}, + {RCU_RD_GPHY1_XRX330, RCU_GFS_ADD1_XRX330}, + {RCU_RD_GPHY2_XRX330, RCU_GFS_ADD2_XRX330}, + {RCU_RD_GPHY3_XRX330, RCU_GFS_ADD3_XRX330}, +}; + +static void xrx200_gphy_boot_addr(struct ltq_gphy_reset *phy_regs, + dma_addr_t dev_addr) +{ + ltq_rcu_w32_mask(0, phy_regs->rd, RCU_RST_REQ); + ltq_rcu_w32(dev_addr, phy_regs->addr); + ltq_rcu_w32_mask(phy_regs->rd, 0, RCU_RST_REQ); +} + /* reset and boot a gphy. these phys only exist on xrx200 SoC */ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr) { @@ -86,23 +147,34 @@ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr) return -EINVAL; } - clk = clk_get_sys("1f203000.rcu", "gphy"); - if (IS_ERR(clk)) - return PTR_ERR(clk); - - clk_enable(clk); - - if (id > 1) { - dev_err(dev, "%u is an invalid gphy id\n", id); - return -EINVAL; + if (of_machine_is_compatible("lantiq,vr9")) { + clk = clk_get_sys("1f203000.rcu", "gphy"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clk_enable(clk); } + dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr); - ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | xrx200_gphy[id].rd, - RCU_RST_REQ); - ltq_rcu_w32(dev_addr, xrx200_gphy[id].addr); - ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~xrx200_gphy[id].rd, - RCU_RST_REQ); + if (of_machine_is_compatible("lantiq,vr9")) { + if (id >= ARRAY_SIZE(xrx200_gphy)) { + dev_err(dev, "%u is an invalid gphy id\n", id); + return -EINVAL; + } + xrx200_gphy_boot_addr(&xrx200_gphy[id], dev_addr); + } else if (of_machine_is_compatible("lantiq,ar10")) { + if (id >= ARRAY_SIZE(xrx300_gphy)) { + dev_err(dev, "%u is an invalid gphy id\n", id); + return -EINVAL; + } + xrx200_gphy_boot_addr(&xrx300_gphy[id], dev_addr); + } else if (of_machine_is_compatible("lantiq,grx390")) { + if (id >= ARRAY_SIZE(xrx330_gphy)) { + dev_err(dev, "%u is an invalid gphy id\n", id); + return -EINVAL; + } + xrx200_gphy_boot_addr(&xrx330_gphy[id], dev_addr); + } return 0; } |