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authorJason Wang <jason77.wang@gmail.com>2010-08-21 16:24:05 +0800
committerSascha Hauer <s.hauer@pengutronix.de>2010-08-21 12:22:43 +0200
commit14f0f512ba6f4eccc9b7cf67be47439ed2917afb (patch)
tree6d4169cfbd10c5c7c8b27d7a24c9062432f3ee35 /arch
parent7f67bff58662604874778e6853e5c394f944e554 (diff)
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ARM: imx: set cache line size to 64 bytes for i.MX5
The core of i.MX5 series is cortex-A8, its cache line size is 64 bytes instead of 32 bytes. Refer to the OMAP3's selection, we choose 64 bytes for i.MX5, this can increase a little bit performance when perform cache operations. Signed-off-by: Jason Wang <jason77.wang@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/plat-mxc/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 0527e65318f4..6785db4179b8 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -43,6 +43,7 @@ config ARCH_MXC91231
config ARCH_MX5
bool "MX5-based"
select CPU_V7
+ select ARM_L1_CACHE_SHIFT_6
help
This enables support for systems based on the Freescale i.MX51 family