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| author | Magnus Damm <damm@opensource.se> | 2010-02-19 09:33:47 +0000 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-02-22 19:11:23 +0900 |
| commit | 6f26d19fce5907cdd0fd953ac1a1d0b1e6e5982c (patch) | |
| tree | 0d4bc4a7bcdb0b5911807532478533f7fa2ebfbf /arch | |
| parent | 7be85c6eb4462cd973e680d9dcf897a7b5b26165 (diff) | |
| download | linux-6f26d19fce5907cdd0fd953ac1a1d0b1e6e5982c.tar.gz linux-6f26d19fce5907cdd0fd953ac1a1d0b1e6e5982c.tar.bz2 linux-6f26d19fce5907cdd0fd953ac1a1d0b1e6e5982c.zip | |
sh: always enable sh7724 vpu_clk and set to 166MHz on Ecovec
Update the sh7724 processor code to always enable vpu_clk.
On the Ecovec board, set the vpu_clk to 166 Mhz.
The 166MHz setting results in a divide-by-6 setup for
vpu_clk and improves the VPU performance compared to the
power-on-reset/bootloader configuration.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/sh/boards/mach-ecovec24/setup.c | 5 | ||||
| -rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7724.c | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c index 8e3b05f93a65..a17dbb3ac73f 100644 --- a/arch/sh/boards/mach-ecovec24/setup.c +++ b/arch/sh/boards/mach-ecovec24/setup.c @@ -1121,6 +1121,11 @@ static int __init arch_setup(void) gpio_request(GPIO_FN_INTC_IRQ1, NULL); gpio_direction_input(GPIO_FN_INTC_IRQ1); + /* set VPU clock to 166 MHz */ + clk = clk_get(NULL, "vpu_clk"); + clk_set_rate(clk, clk_round_rate(clk, 166000000)); + clk_put(clk); + /* enable I2C device */ i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c index a8a993fc894a..6707061fbf54 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c @@ -159,7 +159,7 @@ struct clk div4_clks[DIV4_NR] = { [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0), - [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0), + [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), }; struct clk div6_clks[] = { |