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| author | Yazen Ghannam <yazen.ghannam@amd.com> | 2019-08-22 00:00:02 +0000 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2019-08-23 16:09:52 +0200 |
| commit | 81f5090db843be897414418c24fe472fa6e082b6 (patch) | |
| tree | 5f8ff7ca5c5d5f8c7ad311caa452f446a3b19a00 /block/blk-softirq.c | |
| parent | 7574729e91468d568cc198de438feb35ef04f41a (diff) | |
| download | linux-81f5090db843be897414418c24fe472fa6e082b6.tar.gz linux-81f5090db843be897414418c24fe472fa6e082b6.tar.bz2 linux-81f5090db843be897414418c24fe472fa6e082b6.zip | |
EDAC/amd64: Support asymmetric dual-rank DIMMs
Future AMD systems will support asymmetric dual-rank DIMMs. These are
DIMMs where the ranks are of different sizes.
The even rank will use the Primary Even Chip Select registers and the
odd rank will use the Secondary Odd Chip Select registers.
Recognize if a Secondary Odd Chip Select is being used. Use the
Secondary Odd Address Mask when calculating the chip select size.
[ bp: move csrow_sec_enabled() to the header, fix CS_ODD define and
tone-down the capitalized words spelling. ]
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Tony Luck <tony.luck@intel.com>
Link: https://lkml.kernel.org/r/20190821235938.118710-8-Yazen.Ghannam@amd.com
Diffstat (limited to 'block/blk-softirq.c')
0 files changed, 0 insertions, 0 deletions