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| author | Boris Brezillon <boris.brezillon@free-electrons.com> | 2015-07-09 22:39:38 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-07-27 18:13:32 -0700 |
| commit | 57d866e606ddf2a0cd51f7140cfd8df1fdaa48f6 (patch) | |
| tree | d416f5f0399391f963b2aa4ffc03d281c3d237ad /drivers/clk/hisilicon | |
| parent | 0817b62cc037a56c5e4238c7eb7522299ea27aef (diff) | |
| download | linux-57d866e606ddf2a0cd51f7140cfd8df1fdaa48f6.tar.gz linux-57d866e606ddf2a0cd51f7140cfd8df1fdaa48f6.tar.bz2 linux-57d866e606ddf2a0cd51f7140cfd8df1fdaa48f6.zip | |
clk: fix some determine_rate implementations
Some determine_rate implementations are not returning an error
when they failed to adapt the rate according to the rate request.
Fix them so that they return an error instead of silently
returning 0.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Tony Lindgren <tony@atomide.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: "Emilio López" <emilio@elopez.com.ar>
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Tero Kristo <t-kristo@ti.com>
CC: Peter De Schrijver <pdeschrijver@nvidia.com>
CC: Prashant Gaikwad <pgaikwad@nvidia.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-omap@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: linux-tegra@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/hisilicon')
| -rw-r--r-- | drivers/clk/hisilicon/clk-hi3620.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index a0674ba6659e..c84ec867a91c 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -316,7 +316,7 @@ static int mmc_clk_determine_rate(struct clk_hw *hw, req->rate = 180000000; req->best_parent_rate = 1440000000; } - return 0; + return -EINVAL; } static u32 mmc_clk_delay(u32 val, u32 para, u32 off, u32 len) |