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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2016-09-06 23:38:44 +0200 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2016-09-14 11:22:49 -0700 |
| commit | ed6f4b518004845f6f830422cc9e3ab4f0284930 (patch) | |
| tree | 5427beacd6dd2dd2f0491fbf06281ad771d6e859 /drivers/clk/meson | |
| parent | dcdcc6602292514b0f82b359f2ff30f2fb9a6305 (diff) | |
| download | linux-ed6f4b518004845f6f830422cc9e3ab4f0284930.tar.gz linux-ed6f4b518004845f6f830422cc9e3ab4f0284930.tar.bz2 linux-ed6f4b518004845f6f830422cc9e3ab4f0284930.zip | |
clk: gxbb: expose MPLL2 clock for use by DT
This exposes the MPLL2 clock as this is one of the input clocks of the
ethernet controller's internal mux.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'drivers/clk/meson')
| -rw-r--r-- | drivers/clk/meson/gxbb.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index ae461b16af75..a05b5f62e580 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -183,7 +183,7 @@ /* CLKID_CLK81 */ #define CLKID_MPLL0 13 #define CLKID_MPLL1 14 -#define CLKID_MPLL2 15 +/* CLKID_MPLL2 */ #define CLKID_DDR 16 #define CLKID_DOS 17 #define CLKID_ISA 18 |