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author | Trond Myklebust <trond.myklebust@primarydata.com> | 2015-04-23 15:16:37 -0400 |
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committer | Trond Myklebust <trond.myklebust@primarydata.com> | 2015-04-23 15:16:37 -0400 |
commit | f139b6c676c7e49b66016b28bf3f8ec5c54be891 (patch) | |
tree | 742f00e431dded1daf642b44f4c199b318f255dc /drivers/clk/qcom/gcc-msm8960.c | |
parent | 21330b667070fd64b2340d8d31c1b0800df78ec8 (diff) | |
parent | d654788e98f74f2df8dfc6079fa314938f739486 (diff) | |
download | linux-f139b6c676c7e49b66016b28bf3f8ec5c54be891.tar.gz linux-f139b6c676c7e49b66016b28bf3f8ec5c54be891.tar.bz2 linux-f139b6c676c7e49b66016b28bf3f8ec5c54be891.zip |
Merge tag 'nfs-rdma-for-4.1-1' of git://git.linux-nfs.org/projects/anna/nfs-rdma
NFS: NFSoRDMA Client Changes
This patch series creates an operation vector for each of the different
memory registration modes. This should make it easier to one day increase
credit limit, rsize, and wsize.
Signed-off-by: Anna Schumaker <Anna.Schumaker@Netapp.com>
Diffstat (limited to 'drivers/clk/qcom/gcc-msm8960.c')
-rw-r--r-- | drivers/clk/qcom/gcc-msm8960.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index b0b562b9ce0e..e60feffc10a1 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -48,6 +48,17 @@ static struct clk_pll pll3 = { }, }; +static struct clk_regmap pll4_vote = { + .enable_reg = 0x34c0, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "pll4_vote", + .parent_names = (const char *[]){ "pll4" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + static struct clk_pll pll8 = { .l_reg = 0x3144, .m_reg = 0x3148, @@ -3023,6 +3034,7 @@ static struct clk_branch rpm_msg_ram_h_clk = { static struct clk_regmap *gcc_msm8960_clks[] = { [PLL3] = &pll3.clkr, + [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, [PLL14] = &pll14.clkr, @@ -3247,6 +3259,7 @@ static const struct qcom_reset_map gcc_msm8960_resets[] = { static struct clk_regmap *gcc_apq8064_clks[] = { [PLL3] = &pll3.clkr, + [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, [PLL14] = &pll14.clkr, |