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| author | Stephen Boyd <sboyd@kernel.org> | 2018-10-18 15:38:51 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-10-18 15:38:51 -0700 |
| commit | faff3d8e852b1450e0e8e8f60c4e9af98549548a (patch) | |
| tree | fc3bc8e7185cc19447cba54e23e6b476f6665ba9 /drivers/clk/renesas/Kconfig | |
| parent | 9710ee14bec9a7ffa385342ffb03f91d274b3d07 (diff) | |
| parent | be783cc8d72bb1e48b50c1838a3afeafad4c91c7 (diff) | |
| download | linux-faff3d8e852b1450e0e8e8f60c4e9af98549548a.tar.gz linux-faff3d8e852b1450e0e8e8f60c4e9af98549548a.tar.bz2 linux-faff3d8e852b1450e0e8e8f60c4e9af98549548a.zip | |
Merge branch 'clk-renesas' into clk-next
* clk-renesas: (36 commits)
clk: renesas: r7s9210: Add SPI clocks
clk: renesas: r7s9210: Move table update to separate function
clk: renesas: r7s9210: Convert some clocks to early
clk: renesas: cpg-mssr: Add early clock support
clk: renesas: r8a77970: Add TPU clock
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0
clk: renesas: cpg-mssr: Add r8a774c0 support
clk: renesas: Add r8a774c0 CPG Core Clock Definitions
clk: renesas: r8a7743: Add r8a7744 support
clk: renesas: Add r8a7744 CPG Core Clock Definitions
dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding
dt-bindings: clock: renesas: Convert to SPDX identifiers
clk: renesas: cpg-mssr: Add R7S9210 support
clk: renesas: r8a77970: Add TMU clocks
clk: renesas: r8a77970: Add CMT clocks
clk: renesas: r9a06g032: Fix UART34567 clock rate
clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI
clk: renesas: r8a77980: Add CMT clocks
clk: renesas: r8a77990: Add missing I2C7 clock
...
Diffstat (limited to 'drivers/clk/renesas/Kconfig')
| -rw-r--r-- | drivers/clk/renesas/Kconfig | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index ab2110f96225..b879e3e3a6b4 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -5,11 +5,14 @@ config CLK_RENESAS default y if ARCH_RENESAS select CLK_EMEV2 if ARCH_EMEV2 select CLK_RZA1 if ARCH_R7S72100 + select CLK_R7S9210 if ARCH_R7S9210 select CLK_R8A73A4 if ARCH_R8A73A4 select CLK_R8A7740 if ARCH_R8A7740 - select CLK_R8A7743 if ARCH_R8A7743 + select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744 select CLK_R8A7745 if ARCH_R8A7745 select CLK_R8A77470 if ARCH_R8A77470 + select CLK_R8A774A1 if ARCH_R8A774A1 + select CLK_R8A774C0 if ARCH_R8A774C0 select CLK_R8A7778 if ARCH_R8A7778 select CLK_R8A7779 if ARCH_R8A7779 select CLK_R8A7790 if ARCH_R8A7790 @@ -47,6 +50,10 @@ config CLK_RZA1 bool "RZ/A1H clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP +config CLK_R7S9210 + bool "RZ/A2 clock support" if COMPILE_TEST + select CLK_RENESAS_CPG_MSSR + config CLK_R8A73A4 bool "R-Mobile APE6 clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP @@ -69,6 +76,14 @@ config CLK_R8A77470 bool "RZ/G1C clock support" if COMPILE_TEST select CLK_RCAR_GEN2_CPG +config CLK_R8A774A1 + bool "RZ/G2M clock support" if COMPILE_TEST + select CLK_RCAR_GEN3_CPG + +config CLK_R8A774C0 + bool "RZ/G2E clock support" if COMPILE_TEST + select CLK_RCAR_GEN3_CPG + config CLK_R8A7778 bool "R-Car M1A clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP |