diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-03-15 10:43:57 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-03-21 17:34:53 +0100 |
| commit | f32b0696eabd7a9dc6efd6a97448742d5f2a7db0 (patch) | |
| tree | 3b70e7fea3fdadd88fea733c7b758e935b2f1659 /drivers/clk/renesas/clk-r8a7740.c | |
| parent | b86b493eb29120b82ba919e2653c863c0b3804d6 (diff) | |
| download | linux-f32b0696eabd7a9dc6efd6a97448742d5f2a7db0.tar.gz linux-f32b0696eabd7a9dc6efd6a97448742d5f2a7db0.tar.bz2 linux-f32b0696eabd7a9dc6efd6a97448742d5f2a7db0.zip | |
clk: renesas: r8a7740: Always use readl()/writel()
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel(). Hence use the generic readl()/writel()
instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/clk/renesas/clk-r8a7740.c')
| -rw-r--r-- | drivers/clk/renesas/clk-r8a7740.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/renesas/clk-r8a7740.c b/drivers/clk/renesas/clk-r8a7740.c index 2f7ce6696b6c..d074f8e982d0 100644 --- a/drivers/clk/renesas/clk-r8a7740.c +++ b/drivers/clk/renesas/clk-r8a7740.c @@ -98,20 +98,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, * clock implementation and we currently have no need to change * the multiplier value. */ - u32 value = clk_readl(cpg->reg + CPG_FRQCRC); + u32 value = readl(cpg->reg + CPG_FRQCRC); parent_name = "system"; mult = ((value >> 24) & 0x7f) + 1; } else if (!strcmp(name, "pllc1")) { - u32 value = clk_readl(cpg->reg + CPG_FRQCRA); + u32 value = readl(cpg->reg + CPG_FRQCRA); parent_name = "system"; mult = ((value >> 24) & 0x7f) + 1; div = 2; } else if (!strcmp(name, "pllc2")) { - u32 value = clk_readl(cpg->reg + CPG_PLLC2CR); + u32 value = readl(cpg->reg + CPG_PLLC2CR); parent_name = "system"; mult = ((value >> 24) & 0x3f) + 1; } else if (!strcmp(name, "usb24s")) { - u32 value = clk_readl(cpg->reg + CPG_USBCKCR); + u32 value = readl(cpg->reg + CPG_USBCKCR); if (value & BIT(7)) /* extal2 */ parent_name = of_clk_get_parent_name(np, 1); |