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| author | Hoan Nguyen An <na-hoan@jinso.co.jp> | 2018-08-24 13:52:29 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-08-28 11:06:11 +0200 |
| commit | bc7133cef81283d48a426604ef4af1507e2b20d9 (patch) | |
| tree | d83d37c854bfa2558ef30cce55a4080bcd9fcedf /drivers/clk/renesas/r8a77965-cpg-mssr.c | |
| parent | 331a53e05b67b40a107e7e2597d22b4f8a2ca0d2 (diff) | |
| download | linux-bc7133cef81283d48a426604ef4af1507e2b20d9.tar.gz linux-bc7133cef81283d48a426604ef4af1507e2b20d9.tar.bz2 linux-bc7133cef81283d48a426604ef4af1507e2b20d9.zip | |
clk: renesas: r8a77965: Add FDP clock
This patch adds FDP1-0 clock to the R8A77965 SoC.
Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a77965-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 312f9fe738e3..1fcc411502da 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { + DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1), DEF_MOD("scif5", 202, R8A77965_CLK_S3D4), DEF_MOD("scif4", 203, R8A77965_CLK_S3D4), DEF_MOD("scif3", 204, R8A77965_CLK_S3D4), |