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| author | Katsuhiro Suzuki <katsuhiro@katsuster.net> | 2018-11-18 13:16:12 +0900 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2018-11-19 14:39:29 +0100 |
| commit | 5c73ac2f8b70834a603eb2d92eb0bb464634420b (patch) | |
| tree | a78c64306bdf28fa1d3f7f7b50fb796be0cc0588 /drivers/clk/rockchip | |
| parent | 8989e9d2e6484fe2131dd16fa31698154affef40 (diff) | |
| download | linux-5c73ac2f8b70834a603eb2d92eb0bb464634420b.tar.gz linux-5c73ac2f8b70834a603eb2d92eb0bb464634420b.tar.bz2 linux-5c73ac2f8b70834a603eb2d92eb0bb464634420b.zip | |
clk: rockchip: fix I2S1 clock gate register for rk3328
This patch fixes definition of I2S1 clock gate register for rk3328.
Current setting is not related I2S clocks.
- bit6 of CRU_CLKGATE_CON0 means clk_ddrmon_en
- bit6 of CRU_CLKGATE_CON1 means clk_i2s1_en
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3328.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index 2c5426607790..1eb46aa8b2fa 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -392,7 +392,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { RK3328_CLKGATE_CON(1), 5, GFLAGS, &rk3328_i2s1_fracmux), GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, - RK3328_CLKGATE_CON(0), 6, GFLAGS), + RK3328_CLKGATE_CON(1), 6, GFLAGS), COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0, RK3328_CLKSEL_CON(8), 12, 1, MFLAGS, RK3328_CLKGATE_CON(1), 7, GFLAGS), |