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| author | Stephen Boyd <sboyd@codeaurora.org> | 2016-03-01 10:59:58 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-03-02 17:46:29 -0800 |
| commit | 728f288d2aed7def19a3105ffee3875280a2be2a (patch) | |
| tree | 6578b4403907d661dcedb8678ad39ad4d60e8506 /drivers/clk/samsung/clk-exynos7.c | |
| parent | 2c63935dd634df2d9790adff71876d7140470b70 (diff) | |
| download | linux-728f288d2aed7def19a3105ffee3875280a2be2a.tar.gz linux-728f288d2aed7def19a3105ffee3875280a2be2a.tar.bz2 linux-728f288d2aed7def19a3105ffee3875280a2be2a.zip | |
clk: samsung: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos7.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos7.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 55f8e2e24ab8..ad68d463b12c 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -894,10 +894,8 @@ PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll", /* fixed rate clocks used in the FSYS0 block */ static struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { - FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, - CLK_IS_ROOT, 60000000), - FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, - CLK_IS_ROOT, 125000000), + FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000), + FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000), }; static unsigned long fsys0_clk_regs[] __initdata = { @@ -1009,11 +1007,11 @@ PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" }; /* fixed rate clocks used in the FSYS1 block */ static struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = { FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL, - CLK_IS_ROOT, 300000000), + 0, 300000000), FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL, - CLK_IS_ROOT, 300000000), + 0, 300000000), FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL, - CLK_IS_ROOT, 300000000), + 0, 300000000), }; static unsigned long fsys1_clk_regs[] __initdata = { |