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authorMarek Szyprowski <m.szyprowski@samsung.com>2020-05-06 15:26:59 +0200
committerSylwester Nawrocki <s.nawrocki@samsung.com>2020-05-13 12:42:15 +0200
commit4b159cf13a8a504c1809890121755d04d15b1c22 (patch)
treedd15854eef5a7ae1362c481130679b9f100ca67e /drivers/clk/samsung
parente47bd937e602bb4379546095d1bd0b9871fa60c2 (diff)
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clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x
The proper name for CLK_SMMU_FIMCL3 is "smmu_fimcl3". Remove obvious typo. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index edb2363c735a..fea33399a632 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1165,7 +1165,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
CLK_IS_CRITICAL, 0),
GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13,
CLK_IS_CRITICAL, 0),
- GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
+ GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3", "dout_gscl_blk_333",
GATE_IP_GSCL1, 16, 0, 0),
GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
GATE_IP_GSCL1, 17, 0, 0),