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| author | Tero Kristo <t-kristo@ti.com> | 2016-03-16 21:54:56 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-04-15 17:26:51 -0700 |
| commit | 3db5ca27c80c15d20d0f1152dc34a5bcfa432ae6 (patch) | |
| tree | 493e1efb87c4302d9aca7bd68c77f6b3f5b0a8a6 /drivers/clk/ti | |
| parent | c5cc2a0bc930f1ae00b198aeb752acc3bdd4d5a7 (diff) | |
| download | linux-3db5ca27c80c15d20d0f1152dc34a5bcfa432ae6.tar.gz linux-3db5ca27c80c15d20d0f1152dc34a5bcfa432ae6.tar.bz2 linux-3db5ca27c80c15d20d0f1152dc34a5bcfa432ae6.zip | |
clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
max-rate parameter based on the DPLL types.
[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/ti')
| -rw-r--r-- | drivers/clk/ti/dpll.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index 3bc9959f71c3..9fc8754a6e61 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -655,6 +655,7 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 1000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -674,6 +675,7 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node) .max_divider = 256, .min_divider = 2, .flags = DPLL_J_TYPE, + .max_rate = 2000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -692,6 +694,7 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node) .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 2000000000, .flags = DPLL_J_TYPE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -712,6 +715,7 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node) .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 1000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -729,6 +733,7 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node) .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 1000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; |