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| author | Baoyou Xie <baoyou.xie@linaro.org> | 2017-02-09 11:12:56 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-02-10 09:17:38 -0800 |
| commit | 48239135dd3fd4c5e90ae74cba79d798a9792238 (patch) | |
| tree | f6bb890674c0443044922ddfd58c2b646a33d76c /drivers/clk/zte | |
| parent | 09bdcd6e1784da3d14b3b8d4b6760610dffeb269 (diff) | |
| download | linux-48239135dd3fd4c5e90ae74cba79d798a9792238.tar.gz linux-48239135dd3fd4c5e90ae74cba79d798a9792238.tar.bz2 linux-48239135dd3fd4c5e90ae74cba79d798a9792238.zip | |
clk: zte: add i2s clocks for zx296718
The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/zte')
| -rw-r--r-- | drivers/clk/zte/clk-zx296718.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c index ad5d1dfb3682..2f7c668643fe 100644 --- a/drivers/clk/zte/clk-zx296718.c +++ b/drivers/clk/zte/clk-zx296718.c @@ -936,6 +936,10 @@ static struct zx_clk_gate audio_gate_clk[] = { GATE(AUDIO_I2S1_WCLK, "i2s1_wclk", "i2s1_wclk_div", AUDIO_I2S1_CLK, 9, CLK_SET_RATE_PARENT, 0), GATE(AUDIO_I2S2_WCLK, "i2s2_wclk", "i2s2_wclk_div", AUDIO_I2S2_CLK, 9, CLK_SET_RATE_PARENT, 0), GATE(AUDIO_I2S3_WCLK, "i2s3_wclk", "i2s3_wclk_div", AUDIO_I2S3_CLK, 9, CLK_SET_RATE_PARENT, 0), + GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0), + GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0), + GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0), + GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0), GATE(AUDIO_I2C0_WCLK, "i2c0_wclk", "i2c0_wclk_mux", AUDIO_I2C0_CLK, 9, CLK_SET_RATE_PARENT, 0), GATE(AUDIO_SPDIF0_WCLK, "spdif0_wclk", "spdif0_wclk_div", AUDIO_SPDIF0_CLK, 9, CLK_SET_RATE_PARENT, 0), GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div", AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0), |