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authorSekhar Nori <nsekhar@ti.com>2018-05-25 13:11:45 -0500
committerMichael Turquette <mturquette@baylibre.com>2018-05-30 12:48:27 -0700
commit7f02f18e7f87831747aaa2685f63d16fb2649c6a (patch)
treeadac6daea157c91d4db8fe86c582ebd4a9e26900 /drivers/clk
parent715478bb63ffd76cf90f6536be8592e3f6df9567 (diff)
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clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot be disabled. Mark it so to prevent unused clock disable infrastructure from disabling it. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20180525181150.17873-5-david@lechnology.com
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/davinci/pll-dm646x.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/davinci/pll-dm646x.c b/drivers/clk/davinci/pll-dm646x.c
index a61cc3256418..0ae827e3ce80 100644
--- a/drivers/clk/davinci/pll-dm646x.c
+++ b/drivers/clk/davinci/pll-dm646x.c
@@ -72,7 +72,7 @@ static const struct davinci_pll_clk_info dm646x_pll2_info = {
.flags = 0,
};
-SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
+SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED);
int dm646x_pll2_init(struct device *dev, void __iomem *base)
{