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| author | Paul Cercueil <paul@crapouillou.net> | 2019-01-25 12:34:36 -0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-02-05 13:32:26 -0800 |
| commit | b7e29924a1a628aec60d18651b493fa1601bf944 (patch) | |
| tree | 1ff184e0917cf778baee0daa585722c762ef1b34 /drivers/clk | |
| parent | bfeffd155283772bbe78c6a05dec7c0128ee500c (diff) | |
| download | linux-b7e29924a1a628aec60d18651b493fa1601bf944.tar.gz linux-b7e29924a1a628aec60d18651b493fa1601bf944.tar.bz2 linux-b7e29924a1a628aec60d18651b493fa1601bf944.zip | |
clk: ingenic: jz4740: Fix gating of UDC clock
The UDC clock is gated when the bit is cleared, not when it is set.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Fixes: 2b555a4b9cae ("clk: ingenic: Add missing flag for UDC clock")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/ingenic/jz4740-cgu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index 4479c102e899..b86edd328249 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -165,7 +165,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, .mux = { CGU_REG_CPCCR, 29, 1 }, .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, - .gate = { CGU_REG_SCR, 6 }, + .gate = { CGU_REG_SCR, 6, true }, }, /* Gate-only clocks */ |