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| author | Vincent Minet <vincent@vincent-minet.net> | 2014-07-05 01:51:33 +0200 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2014-07-07 01:24:24 +0200 |
| commit | 179e8471673ce0249cd4ecda796008f7757e5bad (patch) | |
| tree | ebeb2a6091ccb06272177d147643f95ac345daa5 /drivers/cpufreq | |
| parent | 41629a8233470325bfbb60377f555f9e8acc879f (diff) | |
| download | linux-179e8471673ce0249cd4ecda796008f7757e5bad.tar.gz linux-179e8471673ce0249cd4ecda796008f7757e5bad.tar.bz2 linux-179e8471673ce0249cd4ecda796008f7757e5bad.zip | |
intel_pstate: Set CPU number before accessing MSRs
Ensure that cpu->cpu is set before writing MSR_IA32_PERF_CTL during CPU
initialization. Otherwise only cpu0 has its P-state set and all other
cores are left with their values unchanged.
In most cases, this is not too serious because the P-states will be set
correctly when the timer function is run. But when the default governor
is set to performance, the per-CPU current_pstate stays the same forever
and no attempts are made to write the MSRs again.
Signed-off-by: Vincent Minet <vincent@vincent-minet.net>
Cc: All applicable <stable@vger.kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/cpufreq')
| -rw-r--r-- | drivers/cpufreq/intel_pstate.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 127ead814619..86631cb6f7de 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -700,9 +700,8 @@ static int intel_pstate_init_cpu(unsigned int cpunum) cpu = all_cpu_data[cpunum]; - intel_pstate_get_cpu_pstates(cpu); - cpu->cpu = cpunum; + intel_pstate_get_cpu_pstates(cpu); init_timer_deferrable(&cpu->timer); cpu->timer.function = intel_pstate_timer_func; |