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| author | Srikanth, Jampala <Jampala.Srikanth@cavium.com> | 2018-12-04 12:55:54 +0000 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2018-12-13 18:24:39 +0800 |
| commit | cf718eaa8f9b2cb8a372dcfd5ef701188e233558 (patch) | |
| tree | 507e4777d71aa728dd0da7343d696aedebdda2b9 /drivers/crypto/cavium/nitrox/nitrox_isr.c | |
| parent | 19c11c97c39f5c6280b4d523ea170ef9a8f7ed12 (diff) | |
| download | linux-cf718eaa8f9b2cb8a372dcfd5ef701188e233558.tar.gz linux-cf718eaa8f9b2cb8a372dcfd5ef701188e233558.tar.bz2 linux-cf718eaa8f9b2cb8a372dcfd5ef701188e233558.zip | |
crypto: cavium/nitrox - Enabled Mailbox support
Enabled the PF->VF Mailbox support. Mailbox message are interpreted
as {type, opcode, data}. Supported message types are REQ, ACK and NACK.
Signed-off-by: Srikanth Jampala <Jampala.Srikanth@cavium.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/cavium/nitrox/nitrox_isr.c')
| -rw-r--r-- | drivers/crypto/cavium/nitrox/nitrox_isr.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/crypto/cavium/nitrox/nitrox_isr.c b/drivers/crypto/cavium/nitrox/nitrox_isr.c index c5b797808680..3dec570a190a 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_isr.c +++ b/drivers/crypto/cavium/nitrox/nitrox_isr.c @@ -7,6 +7,7 @@ #include "nitrox_csr.h" #include "nitrox_common.h" #include "nitrox_hal.h" +#include "nitrox_mbx.h" /** * One vector for each type of ring @@ -220,7 +221,8 @@ static void nps_core_int_tasklet(unsigned long data) */ static irqreturn_t nps_core_int_isr(int irq, void *data) { - struct nitrox_device *ndev = data; + struct nitrox_q_vector *qvec = data; + struct nitrox_device *ndev = qvec->ndev; union nps_core_int_active core_int; core_int.value = nitrox_read_csr(ndev, NPS_CORE_INT_ACTIVE); @@ -246,6 +248,10 @@ static irqreturn_t nps_core_int_isr(int irq, void *data) if (core_int.s.bmi) clear_bmi_err_intr(ndev); + /* Mailbox interrupt */ + if (core_int.s.mbox) + nitrox_pf2vf_mbox_handler(ndev); + /* If more work callback the ISR, set resend */ core_int.s.resend = 1; nitrox_write_csr(ndev, NPS_CORE_INT_ACTIVE, core_int.value); |